Patch "x86, pmem: Fix cache flushing for iovec write < 8 bytes" has been added to the 4.10-stable tree

This is a note to let you know that I've just added the patch titled

x86, pmem: Fix cache flushing for iovec write < 8 bytes

to the 4.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
x86-pmem-fix-cache-flushing-for-iovec-write-8-bytes.patch
and it can be found in the queue-4.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Ben Hutchings <[email protected]>
Date: Tue, 9 May 2017 18:00:43 +0100
Subject: x86, pmem: Fix cache flushing for iovec write < 8 bytes

From: Ben Hutchings <[email protected]>

commit 8376efd31d3d7c44bd05be337adde023cc531fa1 upstream.

Commit 11e63f6d920d added cache flushing for unaligned writes from an iovec, covering the first and last cache line of a >= 8 byte write and the first cache line of a < 8 byte write. But an unaligned write of 2-7 bytes can still cover two cache lines, so make sure we flush both in that case.

---
 arch/x86/include/asm/pmem.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

@@ -103,7 +103,7 @@ static inline size_t arch_copy_from_iter
 
 		if (bytes < 8) {
 			if (!IS_ALIGNED(dest, 4) || (bytes != 4))
-				arch_wb_cache_pmem(addr, 1);
+				arch_wb_cache_pmem(addr, bytes);
 		} else {
 			if (!IS_ALIGNED(dest, 8)) {
 				dest = ALIGN(dest, boot_cpu_data.x86_clflush_size);

Patches currently in stable-queue which might be from [email protected] are

queue-4.10/x86-pmem-fix-cache-flushing-for-iovec-write-8-bytes.patch