Pull request: u-boot-sunxi/master

Hi Tom,

Please pull this PR.

thanks!
Jagan.

The following changes since commit 24796d27be0d0f403ed6ad7e3022b33e36ac08b5:

Merge git://git.denx.de/u-boot-ubi (2017-06-06 07:13:39 -0400)

are available in the git repository at:

git://git.denx.de/u-boot-sunxi.git master

for you to fetch changes up to 2b1a33213e810f43f9d7e33b9d8db99e1b80a1c0:

sun50i: h5: Add initial NanoPi NEO2 support (2017-06-14 20:25:56 +0530)

----------------------------------------------------------------
Chen-Yu Tsai (1):
sunxi: psci: Move entry address setting to separate function

Icenowy Zheng (12):
sunxi: makes an invisible option for H3-like DRAM controllers
sunxi: Rename bus-width related macros in H3 DRAM code
sunxi: add option for 16-bit DW DRAM controller
sunxi: add bank detection code to H3 DRAM initialization code
sunxi: Add selective DRAM type and timing
sunxi: enable dual rank detection in DesignWare-like DRAM code
sunxi: add support for the DDR2 in V3s SoC
sunxi: add support for V3s DRAM controller
sunxi: enable DRAM initialization and SPL for V3s SoC
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller
sunxi: add LPDDR3 timing from stock boot0
sunxi: add a defconfig for SoPine w/ official baseboard

Jagan Teki (4):
sun8i: h3: Add initial NanoPi M1 Plus support
sun50i: h5: Add initial Orangepi Zero Plus 2 support
sun50i: a64: Add initial Orangepi Win/WinPlus support
sun50i: h5: Add initial NanoPi NEO2 support

 arch/arm/cpu/armv7/sunxi/psci.c                    |  25 ++-
 arch/arm/dts/Makefile                              |   6 +-
 arch/arm/dts/sun50i-a64-orangepi-win.dts           |  94 +++++++++++
 arch/arm/dts/sun50i-h5-nanopi-neo2.dts             |  86 ++++++++++
 arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts     |  97 +++++++++++
 arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts           |  64 +++++++
 arch/arm/include/asm/arch-sunxi/dram.h             |   6 +-
 .../{dram_sun8i_h3.h => dram_sunxi_dw.h}           |  36 +++-
 arch/arm/mach-sunxi/Kconfig                        |  75 ++++++++-
 arch/arm/mach-sunxi/Makefile                       |   5 +-
 .../{dram_sun8i_h3.c => dram_sunxi_dw.c}           | 187 +++++++--------------
 arch/arm/mach-sunxi/dram_timings/Makefile          |   3 +
 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c        |  84 +++++++++
 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c       |  87 ++++++++++
 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c    |  83 +++++++++
 board/sunxi/MAINTAINERS                            |  25 +++
 configs/nanopi_m1_plus_defconfig                   |  18 ++
 configs/nanopi_neo2_defconfig                      |  16 ++
 configs/orangepi_win_defconfig                     |  16 ++
 configs/orangepi_zero_plus2_defconfig              |  18 ++
 configs/sopine_baseboard_defconfig                 |  22 +++
 21 files changed, 910 insertions(+), 143 deletions(-)
 create mode 100644 arch/arm/dts/sun50i-a64-orangepi-win.dts
 create mode 100644 arch/arm/dts/sun50i-h5-nanopi-neo2.dts
 create mode 100644 arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts
 create mode 100644 arch/arm/dts/sun8i-h3-nanopi-m1-plus.dts
 rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (86%)
 rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (84%)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c
 create mode 100644 arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c
 create mode 100644 configs/nanopi_m1_plus_defconfig
 create mode 100644 configs/nanopi_neo2_defconfig
 create mode 100644 configs/orangepi_win_defconfig
 create mode 100644 configs/orangepi_zero_plus2_defconfig
 create mode 100644 configs/sopine_baseboard_defconfig

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Quoted 23 lines · On Fri, 16 Jun 2017 21:54:47 +0530 Jagan Teki <[email protected]> wrote:

Hi Tom,

Please pull this PR.

thanks!
Jagan.

The following changes since commit 24796d27be0d0f403ed6ad7e3022b33e36ac08b5:

Merge git://git.denx.de/u-boot-ubi (2017-06-06 07:13:39 -0400)

are available in the git repository at:

git://git.denx.de/u-boot-sunxi.git master

for you to fetch changes up to 2b1a33213e810f43f9d7e33b9d8db99e1b80a1c0:

sun50i: h5: Add initial NanoPi NEO2 support (2017-06-14 20:25:56 +0530)

----------------------------------------------------------------
Chen-Yu Tsai (1):
sunxi: psci: Move entry address setting to separate function

Quoted 13 lines

Icenowy Zheng (12):
sunxi: makes an invisible option for H3-like DRAM controllers
sunxi: Rename bus-width related macros in H3 DRAM code
sunxi: add option for 16-bit DW DRAM controller
sunxi: add bank detection code to H3 DRAM initialization code
sunxi: Add selective DRAM type and timing
sunxi: enable dual rank detection in DesignWare-like DRAM code
sunxi: add support for the DDR2 in V3s SoC
sunxi: add support for V3s DRAM controller
sunxi: enable DRAM initialization and SPL for V3s SoC
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller
sunxi: add LPDDR3 timing from stock boot0
sunxi: add a defconfig for SoPine w/ official baseboard

Isn't this rather invasive change (a) still under review and (b) scheduled for the next merge window either way?

Hi Tom,

Please pull this PR.

thanks!
Jagan.

The following changes since commit 24796d27be0d0f403ed6ad7e3022b33e36ac08b5:

Merge git://git.denx.de/u-boot-ubi (2017-06-06 07:13:39 -0400)

are available in the git repository at:

git://git.denx.de/u-boot-sunxi.git master

for you to fetch changes up to 2b1a33213e810f43f9d7e33b9d8db99e1b80a1c0:

sun50i: h5: Add initial NanoPi NEO2 support (2017-06-14 20:25:56 +0530)

----------------------------------------------------------------
Chen-Yu Tsai (1):
sunxi: psci: Move entry address setting to separate function

Icenowy Zheng (12):
sunxi: makes an invisible option for H3-like DRAM controllers
sunxi: Rename bus-width related macros in H3 DRAM code
sunxi: add option for 16-bit DW DRAM controller
sunxi: add bank detection code to H3 DRAM initialization code
sunxi: Add selective DRAM type and timing
sunxi: enable dual rank detection in DesignWare-like DRAM code
sunxi: add support for the DDR2 in V3s SoC
sunxi: add support for V3s DRAM controller
sunxi: enable DRAM initialization and SPL for V3s SoC
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller
sunxi: add LPDDR3 timing from stock boot0
sunxi: add a defconfig for SoPine w/ official baseboard

Jagan Teki (4):
sun8i: h3: Add initial NanoPi M1 Plus support
sun50i: h5: Add initial Orangepi Zero Plus 2 support
sun50i: a64: Add initial Orangepi Win/WinPlus support
sun50i: h5: Add initial NanoPi NEO2 support

Hi Tom,

Please pull this PR.

thanks!
Jagan.

The following changes since commit 24796d27be0d0f403ed6ad7e3022b33e36ac08b5:

Merge git://git.denx.de/u-boot-ubi (2017-06-06 07:13:39 -0400)

are available in the git repository at:

git://git.denx.de/u-boot-sunxi.git master

for you to fetch changes up to 2b1a33213e810f43f9d7e33b9d8db99e1b80a1c0:

sun50i: h5: Add initial NanoPi NEO2 support (2017-06-14 20:25:56 +0530)