Patch "clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition" has been added to the 4.11-stable tree

This is a note to let you know that I've just added the patch titled

clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition

to the 4.11-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
clk-sunxi-ng-sun5i-fix-ahb_bist_clk-definition.patch
and it can be found in the queue-4.11 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Boris Brezillon <[email protected]>
Date: Wed, 24 May 2017 18:34:29 +0200
Subject: clk: sunxi-ng: sun5i: Fix ahb_bist_clk definition

From: Boris Brezillon <[email protected]>

commit 370d9192719e6c174167888cf9240df2542e3b4b upstream.

AHB BIST gate is actually controlled with bit 7.

This bug was detected while trying to use the NAND controller which is using the DMA engine to transfer data to the NAND.
Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit, the core was disabling the DMA engine clock as part of its 'disable unused clks' procedure, which was causing all DMA transfers to fail after this point.

---
 drivers/clk/sunxi-ng/ccu-sun5i.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

@@ -243,7 +243,7 @@ static SUNXI_CCU_GATE(ahb_ss_clk,	"ahb-s
 static SUNXI_CCU_GATE(ahb_dma_clk,	"ahb-dma",	"ahb",
 		      0x060, BIT(6), 0);
 static SUNXI_CCU_GATE(ahb_bist_clk,	"ahb-bist",	"ahb",
-		      0x060, BIT(6), 0);
+		      0x060, BIT(7), 0);
 static SUNXI_CCU_GATE(ahb_mmc0_clk,	"ahb-mmc0",	"ahb",
 		      0x060, BIT(8), 0);
 static SUNXI_CCU_GATE(ahb_mmc1_clk,	"ahb-mmc1",	"ahb",

Patches currently in stable-queue which might be from [email protected] are

queue-4.11/clk-sunxi-ng-sun5i-fix-ahb_bist_clk-definition.patch