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FAILED: patch "[PATCH] drm/i915: Fix scaler init during CRTC HW state readout" failed to apply to 4.4-stable tree

PATCH [email protected] 1 participant 1 message Aug 1, 2017

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The patch below does not apply to the 4.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From 283d6860d64f5091565bf729b0a6d6af14ae6c27 Mon Sep 17 00:00:00 2001

From: Imre Deak <[email protected]>
Date: Thu, 20 Jul 2017 14:28:20 +0300
Subject: [PATCH] drm/i915: Fix scaler init during CRTC HW state readout
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The scaler allocation code depends on a non-zero default value for the crtc scaler_id, so make sure we initialize the scaler state accordingly even if the crtc is off. This fixes at least an initial YUV420 modeset (added in a follow-up patchset by Shashank) when booting with the screen
off: after the initial HW readout and modeset which enables the scaler a subsequent modeset will disable the scaler which isn't properly allocated. This results in a funky HW state where the pipe scaler HW registers can't be modified and the normally black screen is grey and shifted to the right or jitters.

The problem was revealed by Shashank's YUV420 patchset and first reported by Ville.

v2:
- In the stable tag also include versions which need backporting (Jani)

Cc Jani Nikula <[email protected]>
Cc Shashank Sharma <[email protected]>
Cc Ville Syrjälä <[email protected]>
Cc Chandra Konduru <[email protected]>
Cc Matt Roper <[email protected]>
Cc <[email protected]> # 4.2.x
Fixes a1b2278e4dfc ("drm/i915: skylake panel fitting using shared scalers")
(cherry picked from commit 5fb9dadf336f3590c799e8cbde348215dccc2aa2)
drivers/gpu/drm/i915/intel_display.c +7 -7
index e35daae00137..9471c88d449e 100644
@@ -9093,6 +9093,13 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	u64 power_domain_mask;
 	bool active;
 
+	if (INTEL_GEN(dev_priv) >= 9) {
+		intel_crtc_init_scalers(crtc, pipe_config);
+
+		pipe_config->scaler_state.scaler_id = -1;
+		pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
+	}
+
 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
 	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 		return false;
@@ -9121,13 +9128,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
 	pipe_config->gamma_mode =
 		I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
 
-	if (INTEL_GEN(dev_priv) >= 9) {
-		intel_crtc_init_scalers(crtc, pipe_config);
-
-		pipe_config->scaler_state.scaler_id = -1;
-		pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
-	}
-
 	power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
 	if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
 		power_domain_mask |= BIT_ULL(power_domain);