Patch "mmc: sunxi: Keep default timing phase settings for new timing mode" has been added to the 4.12-stable tree

This is a note to let you know that I've just added the patch titled

mmc: sunxi: Keep default timing phase settings for new timing mode

to the 4.12-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
mmc-sunxi-keep-default-timing-phase-settings-for-new-timing-mode.patch
and it can be found in the queue-4.12 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Chen-Yu Tsai <[email protected]>
Date: Fri, 14 Jul 2017 14:42:55 +0800
Subject: mmc: sunxi: Keep default timing phase settings for new timing mode

From: Chen-Yu Tsai <[email protected]>

commit 26cb2be4c7c42644ccd147c786edb9006300ee56 upstream.

The register for the "new timing mode" also has bit fields for setting output and sample timing phases. According to comments in Allwinner's BSP kernel, the default values are good enough.

Keep the default values already in the hardware when setting new timing mode, instead of overwriting the whole register.

controllers")

---
 drivers/mmc/host/sunxi-mmc.c |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

@@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct
 	}
 	mmc_writel(host, REG_CLKCR, rval);
 
-	if (host->cfg->needs_new_timings)
-		mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
+	if (host->cfg->needs_new_timings) {
+		/* Don't touch the delay bits */
+		rval = mmc_readl(host, REG_SD_NTSR);
+		rval |= SDXC_2X_TIMING_MODE;
+		mmc_writel(host, REG_SD_NTSR, rval);
+	}
 
 	ret = sunxi_mmc_clk_set_phase(host, ios, rate);
 	if (ret)

Patches currently in stable-queue which might be from [email protected] are

queue-4.12/mmc-sunxi-keep-default-timing-phase-settings-for-new-timing-mode.patch