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Patch "drm/msm: Ensure that the hardware write pointer is valid" has been added to the 4.9-stable tree

PATCH [email protected] 1 participant 1 message Aug 4, 2017

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This is a note to let you know that I've just added the patch titled

drm/msm: Ensure that the hardware write pointer is valid

to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
drm-msm-ensure-that-the-hardware-write-pointer-is-valid.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From foo@baz Fri Aug 4 13:32:40 PDT 2017

From: Jordan Crouse <[email protected]>
Date: Tue, 20 Dec 2016 08:54:29 -0700
Subject: drm/msm: Ensure that the hardware write pointer is valid

From: Jordan Crouse <[email protected]>

[ Upstream commit 88b333b0ed790f9433ff542b163bf972953b74d3 ]

Currently the value written to CP_RB_WPTR is calculated on the fly as (rb->next - rb->start). But as the code is designed rb->next is wrapped before writing the commands so if a series of commands happened to fit perfectly in the ringbuffer, rb->next would end up being equal to rb->size / 4 and thus result in an out of bounds address to CP_RB_WPTR.

The easiest way to fix this is to mask WPTR when writing it to the hardware; it makes the hardware happy and the rest of the ringbuffer math appears to work and there isn't any point in upsetting anything.

[squash in is_power_of_2() check]
---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c |    9 ++++++++-
 drivers/gpu/drm/msm/msm_ringbuffer.c    |    3 ++-
 2 files changed, 10 insertions(+), 2 deletions(-)
drivers/gpu/drm/msm/adreno/adreno_gpu.c +8 -1
@@ -210,7 +210,14 @@ void adreno_submit(struct msm_gpu *gpu,
 void adreno_flush(struct msm_gpu *gpu)
 {
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-	uint32_t wptr = get_wptr(gpu->rb);
+	uint32_t wptr;
+
+	/*
+	 * Mask wptr value that we calculate to fit in the HW range. This is
+	 * to account for the possibility that the last command fit exactly into
+	 * the ringbuffer and rb->next hasn't wrapped to zero yet
+	 */
+	wptr = get_wptr(gpu->rb) & ((gpu->rb->size / 4) - 1);
 
 	/* ensure writes to ringbuffer have hit system memory: */
 	mb();
drivers/gpu/drm/msm/msm_ringbuffer.c +2 -1
@@ -23,7 +23,8 @@ struct msm_ringbuffer *msm_ringbuffer_ne
 	struct msm_ringbuffer *ring;
 	int ret;
 
-	size = ALIGN(size, 4);   /* size should be dword aligned */
+	if (WARN_ON(!is_power_of_2(size)))
+		return ERR_PTR(-EINVAL);
 
 	ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 	if (!ring) {

Patches currently in stable-queue which might be from [email protected] are

queue-4.9/drm-msm-verify-that-msm_submit_bo_flags-are-set.patch queue-4.9/drm-msm-put-back-the-vaddr-in-submit_reloc.patch queue-4.9/drm-msm-ensure-that-the-hardware-write-pointer-is-valid.patch