Patch "drm: rcar-du: Fix H/V sync signal polarity configuration" has been added to the 4.9-stable tree

This is a note to let you know that I've just added the patch titled

drm: rcar-du: Fix H/V sync signal polarity configuration

to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
drm-rcar-du-fix-h-v-sync-signal-polarity-configuration.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Koji Matsuoka <[email protected]>
Date: Mon, 16 May 2016 11:28:15 +0900
Subject: drm: rcar-du: Fix H/V sync signal polarity configuration

From: Koji Matsuoka <[email protected]>

commit fd1adef3bff0663c5ac31b45bc4a05fafd43d19b upstream.

The VSL and HSL bits in the DSMR register set the corresponding horizontal and vertical sync signal polarity to active high. The code got it the wrong way around, fix it.

---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

@@ -149,8 +149,8 @@ static void rcar_du_crtc_set_display_tim
 	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 
 	/* Signal polarities */
-	value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
-	      | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
+	value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
+	      | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
 	      | DSMR_DIPM_DISP | DSMR_CSPM;
 	rcar_du_crtc_write(rcrtc, DSMR, value);
 

Patches currently in stable-queue which might be from [email protected] are

queue-4.9/drm-rcar-du-fix-h-v-sync-signal-polarity-configuration.patch queue-4.9/drm-rcar-du-fix-display-timing-controller-parameter.patch