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FAILED: patch "[PATCH] MIPS: Fix CM region target definitions" failed to apply to 3.18-stable tree

PATCH [email protected] 1 participant 1 message Nov 5, 2017

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The patch below does not apply to the 3.18-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From 6a6cba1d945a7511cdfaf338526871195e420762 Mon Sep 17 00:00:00 2001

From: Paul Burton <[email protected]>
Date: Tue, 31 Oct 2017 15:09:22 -0700
Subject: [PATCH] MIPS: Fix CM region target definitions

The default CM target field in the GCR_BASE register is encoded with 0 meaning memory & 1 being reserved. However the definitions we use for those bits effectively get these two values backwards - likely because they were copied from the definitions for the CM regions where the target is encoded differently. This results in use setting up GCR_BASE with the reserved target value by default, rather than targeting memory as intended. Although we currently seem to get away with this it's not a great idea to rely upon.

Fix this by changing our macros to match the documentated target values.

The incorrect encoding became used as of commit 9f98f3dd0c51 ("MIPS: Add generic CM probe & access code") in the Linux v3.15 cycle, and was likely carried forwards from older but unused code introduced by commit 39b8d5254246 ("[MIPS] Add support for MIPS CMP platform.") in the v2.6.26 cycle.

Fixes 9f98f3dd0c51 ("MIPS: Add generic CM probe & access code")
Cc Matt Redfearn <[email protected]>
Cc Ralf Baechle <[email protected]>
Cc <[email protected]> # v3.15+

Patchwork: https://patchwork.linux-mips.org/patch/17562/

arch/mips/include/asm/mips-cm.h +2 -2
index 3708b8ccc0b4..8bc5df49b0e1 100644
@@ -142,8 +142,8 @@ GCR_ACCESSOR_RO(64, 0x000, config)
 GCR_ACCESSOR_RW(64, 0x008, base)
 #define CM_GCR_BASE_GCRBASE			GENMASK_ULL(47, 15)
 #define CM_GCR_BASE_CMDEFTGT			GENMASK(1, 0)
-#define  CM_GCR_BASE_CMDEFTGT_DISABLED		0
-#define  CM_GCR_BASE_CMDEFTGT_MEM		1
+#define  CM_GCR_BASE_CMDEFTGT_MEM		0
+#define  CM_GCR_BASE_CMDEFTGT_RESERVED		1
 #define  CM_GCR_BASE_CMDEFTGT_IOCU0		2
 #define  CM_GCR_BASE_CMDEFTGT_IOCU1		3