Patch "EDAC, i5000, i5400: Fix definition of NRECMEMB register" has been added to the 4.9-stable tree
Subsystems (4)
This is a note to let you know that I've just added the patch titled
EDAC, i5000, i5400: Fix definition of NRECMEMB register
to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
edac-i5000-i5400-fix-definition-of-nrecmemb-register.patch
and it can be found in the queue-4.9 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
From foo@baz Tue Dec 12 13:26:17 CET 2017
From: Jérémy Lefaure <[email protected]>
Date: Wed, 28 Jun 2017 20:57:29 -0400
Subject: EDAC, i5000, i5400: Fix definition of NRECMEMB register
From: Jérémy Lefaure <[email protected]>
[ Upstream commit a8c8261425649da58bdf08221570e5335ad33a31 ]
In the i5000 and i5400 drivers, the NRECMEMB register is defined as a 16-bit value, which results in wrong shifts in the code, as reported by sparse.
In the datasheets ([1], section 3.9.22.20 and [2], section 3.9.22.21), this register is a 32-bit register. A u32 value for the register fixes the wrong shifts warnings and matches the datasheet.
Also fix the mask to access to the CAS bits [27:16] in the i5000 driver.
[1]: https://www.intel.com/content/dam/doc/datasheet/5000p-5000v-5000z-chipset-memory-controller-hub-datasheet.pdf
[2]: https://www.intel.se/content/dam/doc/datasheet/5400-chipset-memory-controller-hub-datasheet.pdf
--- drivers/edac/i5000_edac.c | 6 +++--- drivers/edac/i5400_edac.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-)
Patches currently in stable-queue which might be from [email protected] are
queue-4.9/edac-i5000-i5400-fix-definition-of-nrecmemb-register.patch queue-4.9/edac-i5000-i5400-fix-use-of-mtr_dram_width-macro.patch --
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drivers/edac/i5000_edac.c +3 -3
@@ -227,7 +227,7 @@#define NREC_RDWR (x) (((x)>>11) & 1)#define NREC_RANK (x) (((x)>>8) & 0x7)#define NRECMEMB 0xC0 -#define NREC_CAS (x) (((x)>>16) & 0xFFFFFF) +#define NREC_CAS (x) (((x)>>16) & 0xFFF)#define NREC_RAS (x) ((x) & 0x7FFF)#define NRECFGLOG 0xC4#define NREEECFBDA 0xC8
@@ -371,7 +371,7 @@ struct i5000_error_info {/* These registers are input ONLY if there was a * Non-Recoverable Error */ u16 nrecmema;/* Non-Recoverable Mem log A */ -u16 nrecmemb;/* Non-Recoverable Mem log B */ +u32 nrecmemb;/* Non-Recoverable Mem log B */ };
@@ -407,7 +407,7 @@ static void i5000_get_error_info(struct NERR_FAT_FBD, &info->nerr_fat_fbd);pci_read_config_word (pvt->branchmap_werrors,NRECMEMA , &info->nrecmema); -pci_read_config_word (pvt->branchmap_werrors, +pci_read_config_dword (pvt->branchmap_werrors,NRECMEMB , &info->nrecmemb);/* Clear the error bits, by writing them back */
drivers/edac/i5400_edac.c +2 -2
@@ -368,7 +368,7 @@ struct i5400_error_info {/* These registers are input ONLY if there was a Non-Rec Error */ u16 nrecmema;/* Non-Recoverable Mem log A */ -u16 nrecmemb;/* Non-Recoverable Mem log B */ +u32 nrecmemb;/* Non-Recoverable Mem log B */ };
@@ -458,7 +458,7 @@ static void i5400_get_error_info(struct NERR_FAT_FBD, &info->nerr_fat_fbd);pci_read_config_word (pvt->branchmap_werrors,NRECMEMA , &info->nrecmema); -pci_read_config_word (pvt->branchmap_werrors, +pci_read_config_dword (pvt->branchmap_werrors,NRECMEMB , &info->nrecmemb);/* Clear the error bits, by writing them back */