Drivers: gpu: drm: amdgpu: fixed coding style issues

index c04f44a90392..8706792ee826 100644
@@ -587,8 +587,7 @@ static const struct amd_ip_funcs acp_ip_funcs = {
 	.set_powergating_state = acp_set_powergating_state,
 };
 
-const struct amdgpu_ip_block_version acp_ip_block =
-{
+const struct amdgpu_ip_block_version acp_ip_block = {
 	.type = AMD_IP_BLOCK_TYPE_ACP,
 	.major = 2,
 	.minor = 2,

index f450b69323fa..695e2d0199e7 100644
@@ -206,7 +206,7 @@ amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev,
 
 	hpd.gpio = *gpio;
 	if (gpio->reg == reg) {
-		switch(gpio->mask) {
+		switch (gpio->mask) {
 		case (1 << 0):
 			hpd.hpd = AMDGPU_HPD_1;
 			break;

@@ -398,7 +398,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
 							       record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 								switch (record->ucRecordType) {
 								case ATOM_ENCODER_CAP_RECORD_TYPE:
-									cap_record =(ATOM_ENCODER_CAP_RECORD *)
+									cap_record = (ATOM_ENCODER_CAP_RECORD *)
 										record;
 									caps = le16_to_cpu(cap_record->usEncoderCap);
 									break;

@@ -1415,7 +1415,7 @@ static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOL
 {
 	u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
 	u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
-	u8 *start = (u8*)v3;
+	u8 *start = (u8 *)v3;
 
 	while (offset < size) {
 		ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);

index ff8efd0f8fd5..18eccf8c5bcc 100644
@@ -71,7 +71,7 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
 	struct atom_context *ctx = adev->mode_info.atom_context;
 	int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 						vram_usagebyfirmware);
-	struct vram_usagebyfirmware_v2_1 *	firmware_usage;
+	struct vram_usagebyfirmware_v2_1 *firmware_usage;
 	uint32_t start_addr, size;
 	uint16_t data_offset;
 	int usage_bytes = 0;

index c13c51af0b68..7e9f19b3e7f1 100644
@@ -63,19 +63,23 @@ struct atpx_mux {
 	u16 mux;
 } __packed;
 
-bool amdgpu_has_atpx(void) {
+bool amdgpu_has_atpx(void)
+{
 	return amdgpu_atpx_priv.atpx_detected;
 }
 
-bool amdgpu_has_atpx_dgpu_power_cntl(void) {
+bool amdgpu_has_atpx_dgpu_power_cntl(void)
+{
 	return amdgpu_atpx_priv.atpx.functions.power_cntl;
 }
 
-bool amdgpu_is_atpx_hybrid(void) {
+bool amdgpu_is_atpx_hybrid(void)
+{
 	return amdgpu_atpx_priv.atpx.is_hybrid;
 }
 
-bool amdgpu_atpx_dgpu_req_power_for_displays(void) {
+bool amdgpu_atpx_dgpu_req_power_for_displays(void)
+{
 	return amdgpu_atpx_priv.atpx.dgpu_req_power_for_displays;
 }
 

86 lines not on this page · raw message

index df9cbc78e168..685c5b4f790c 100644
@@ -606,10 +606,18 @@ static int amdgpu_connector_set_property(struct drm_connector *connector,
 
 		switch (val) {
 		default:
-		case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
-		case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
-		case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
-		case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
+		case
+			DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF;
+			break;
+		case
+			DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER;
+			break;
+		case
+			DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT;
+			break;
+		case
+			DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL;
+			break;
 		}
 		if (amdgpu_encoder->rmx_type == rmx_type)
 			return 0;

@@ -804,11 +812,19 @@ static int amdgpu_connector_set_lcd_property(struct drm_connector *connector,
 	}
 
 	switch (value) {
-	case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break;
-	case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break;
-	case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break;
+	case
+		DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF;
+		break;
+	case
+		DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER;
+		break;
+	case
+		DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT;
+		break;
 	default:
-	case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break;
+	case
+		DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL;
+		break;
 	}
 	if (amdgpu_encoder->rmx_type == rmx_type)
 		return 0;

@@ -1102,7 +1118,7 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force)
 					/* assume digital unless load detected otherwise */
 					amdgpu_connector->use_digital = true;
 					lret = encoder_funcs->detect(encoder, connector);
-					DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret);
+					DRM_DEBUG_KMS("load_detect %x returned: %x\n", encoder->encoder_type, lret);
 					if (lret == connector_status_connected)
 						amdgpu_connector->use_digital = false;
 				}

@@ -1904,8 +1920,7 @@ amdgpu_connector_add(struct amdgpu_device *adev,
 
 	if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) {
 		if (i2c_bus->valid) {
-			connector->polled = DRM_CONNECTOR_POLL_CONNECT |
-			                    DRM_CONNECTOR_POLL_DISCONNECT;
+			connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
 		}
 	} else
 		connector->polled = DRM_CONNECTOR_POLL_HPD;

index 57abf7abd7a9..3668c3413217 100644
@@ -261,8 +261,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 	time_us = ktime_to_us(ktime_get());
 	increment_us = time_us - adev->mm_stats.last_update_us;
 	adev->mm_stats.last_update_us = time_us;
-	adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
-                                      us_upper_bound);
+	adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us, us_upper_bound);
 
 	/* This prevents the short period of low performance when the VRAM
 	 * usage is low and the driver is in debt or doesn't have enough

@@ -395,7 +394,7 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 	if (!p->evictable)
 		return false;
 
-	for (;&p->evictable->tv.head != &p->validated;
+	for (; &p->evictable->tv.head != &p->validated;
 	     p->evictable = list_prev_entry(p->evictable, tv.head)) {
 
 		struct amdgpu_bo_list_entry *candidate = p->evictable;

@@ -598,7 +597,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 			struct ttm_tt *ttm = e->robj->tbo.ttm;
 
 			e->user_pages = kvmalloc_array(ttm->num_pages,
-							 sizeof(struct page*),
+							 sizeof(struct page *),
 							 GFP_KERNEL | __GFP_ZERO);
 			if (!e->user_pages) {
 				r = -ENOMEM;

@@ -1376,7 +1375,7 @@ int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
 		dma_fence_put(fence);
 		if (r)
 			return r;
-		r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
+		r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
 		drm_syncobj_put(syncobj);
 		return r;
 

index 3573ecdb06ee..05fa2d52af45 100644
@@ -367,7 +367,7 @@ void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 	if (array_size % 3)
 		return;
 
-	for (i = 0; i < array_size; i +=3) {
+	for (i = 0; i < array_size; i += 3) {
 		reg = registers[i + 0];
 		and_mask = registers[i + 1];
 		or_mask = registers[i + 2];

@@ -1157,7 +1157,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
 		dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
 			 amdgpu_sched_jobs);
 		amdgpu_sched_jobs = 4;
-	} else if (!is_power_of_2(amdgpu_sched_jobs)){
+	} else if (!is_power_of_2(amdgpu_sched_jobs)) {
 		dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
 			 amdgpu_sched_jobs);
 		amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);

@@ -1347,7 +1347,7 @@ bool amdgpu_is_idle(struct amdgpu_device *adev,
 
 }
 
-struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
+struct amdgpu_ip_block *amdgpu_get_ip_block(struct amdgpu_device *adev,
 					     enum amd_ip_block_type type)
 {
 	int i;

@@ -1882,7 +1882,7 @@ int amdgpu_suspend(struct amdgpu_device *adev)
 	r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
 					 AMD_CG_STATE_UNGATE);
 	if (r) {
-		DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
+		DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
 	}
 
 	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

@@ -2006,7 +2006,7 @@ static int amdgpu_resume_phase2(struct amdgpu_device *adev)
 			continue;
 		if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
 				adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
-				adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
+				adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)
 			continue;
 		r = adev->ip_blocks[i].version->funcs->resume(adev);
 		if (r) {

@@ -3108,8 +3108,7 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
 	if (r) {
 		/* bad news, how to tell it to userspace ? */
 		dev_info(adev->dev, "GPU reset failed\n");
-	}
-	else {
+	} else {
 		dev_info(adev->dev, "GPU reset successed!\n");
 	}
 

@@ -3680,7 +3679,7 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
 {
 	struct amdgpu_device *adev = f->f_inode->i_private;
 	int r, x;
-	ssize_t result=0;
+	ssize_t result = 0;
 	uint32_t offset, se, sh, cu, wave, simd, data[32];
 
 	if (size & 3 || *pos & 3)