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drm/msm: device tree changes to support devfreq

PATCH New Jordan Crouse 2 participants 3 messages Dec 18, 2017 1 message not in the archive

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#0 lore raw

cover drm/msm: device tree changes to support devfreq

Rob, here are the device tree changes to support the devfreq and speed bin features added in https://patchwork.freedesktop.org/series/34189/.
These are against your wip-8996-drm tree which is pretty much the most recent db820c tree we have.

Jordan Crouse (2):
arm64: dts: Use OPP table for Adreno GPU
arm64: dts: Add full GPU frequency table for 8996

 arch/arm64/boot/dts/qcom/msm8996.dtsi | 59 ++++++++++++++++++++++++++++-------
 1 file changed, 47 insertions(+), 12 deletions(-)
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#2 lore raw

PATCH 1/2 arm64: dts: Use OPP table for Adreno GPU

Add a nvmem cell to let the GPU driver read a speed bin from the fuses (if applicable). Then switch the cpu frequency table definitions to real OPP v2 tables so we can take advantage of the hardware matching mechanism.

---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 34 ++++++++++++++++++++++------------
 1 file changed, 22 insertions(+), 12 deletions(-)
arch/arm64/boot/dts/qcom/msm8996.dtsi +22 -12
index 65fd370..f136d4c 100644
@@ -642,6 +642,11 @@
 				reg = <0x24f 0x1>;
 				bits = <1 4>;
 			};
+
+			gpu_speed_bin: gpu_speed_bin@133 {
+				reg = <0x133 0x1>;
+				bits = <5 3>;
+			};
 		};
 
 		phy@34000 {
@@ -1099,6 +1104,19 @@
 			status = "okay";
 		};
 
+		gpu_opp_table: opp_table {
+			compatible  ="operating-points-v2";
+
+			opp-624000000 {
+				opp-hz = /bits/ 64 <624000000>;
+				opp-supported-hw = <0x01>;
+			};
+			opp-510000000 {
+				opp-hz = /bits/ 64 <510000000>;
+				opp-supported-hw = <0xFF>;
+			};
+		};
+
 		gpu@b00000 {
 			compatible = "qcom,adreno-530.2", "qcom,adreno";
 			#stream-id-cells = <16>;
@@ -1124,21 +1142,13 @@
 			power-domains = <&mmcc GPU_GDSC>;
 			iommus = <&adreno_smmu 0>;
 
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
 			qcom,gpu-quirk-two-pass-use-wfi;
 			qcom,gpu-quirk-fault-detect-mask;
 
-			/* This is a safe speed for bring up in all bin levels.
-			 * This isn't the fastest the chip can go, but we can
-			 * get there eventually */
-			qcom,gpu-pwrlevels {
-				compatible = "qcom,gpu-pwrlevels";
-				qcom,gpu-pwrlevel@0 {
-					qcom,gpu-freq = <624000000>;
-				};
-				qcom,gpu-pwrlevel@1 {
-					qcom,gpu-freq = <27000000>;
-				};
-			};
+			operating-points-v2 = <&gpu_opp_table>;
 
 			zap-shader {
 				memory-region = <&zap_shader_region>;
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#3 lore raw

PATCH 2/2 arm64: dts: Add full GPU frequency table for 8996

In reply to Jordan Crouse

Now that we have frequency scaling for the GPU give it a full list of frequencies it can scale to. The two higher frequencies are for faster binned parts and the remaining frequencies work on all targets.

---
 arch/arm64/boot/dts/qcom/msm8996.dtsi | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
arch/arm64/boot/dts/qcom/msm8996.dtsi +25 -0
index f136d4c..f495a2e 100644
@@ -1107,14 +1107,39 @@
 		gpu_opp_table: opp_table {
 			compatible  ="operating-points-v2";
 
+			/*
+			 * 624Mhz and 560Mhz are only available on speed bin
+			 * (1 << 0). All the rest are available on all bins of
+			 * the hardware
+			 */
 			opp-624000000 {
 				opp-hz = /bits/ 64 <624000000>;
 				opp-supported-hw = <0x01>;
 			};
+			opp-560000000 {
+				opp-hz = /bits/ 64 <560000000>;
+				opp-supported-hw = <0x01>;
+			};
 			opp-510000000 {
 				opp-hz = /bits/ 64 <510000000>;
 				opp-supported-hw = <0xFF>;
 			};
+			opp-401800000 {
+				opp-hz = /bits/ 64 <401800000>;
+				opp-supported-hw = <0xFF>;
+			};
+			opp-315000000 {
+				opp-hz = /bits/ 64 <315000000>;
+				opp-supported-hw = <0xFF>;
+			};
+			opp-214000000 {
+				opp-hz = /bits/ 64 <214000000>;
+				opp-supported-hw = <0xFF>;
+			};
+			opp-133000000 {
+				opp-hz = /bits/ 64 <133000000>;
+				opp-supported-hw = <0xFF>;
+			};
 		};
 
 		gpu@b00000 {
Signature · 1 line
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