mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL

PATCH New Fabio Estevam 3 participants 4 messages Jan 2, 2018 – Jan 12, 2018

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Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape

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Fabio Estevam

author reviewer

2018-01-02 00:51 UTC #0 lore raw

PATCH 1/1 mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL

From: Fabio Estevam <[email protected]>

i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to access it.

Signed-off-by Fabio Estevam <[email protected]>

---
 arch/arm/mach-imx/mx6/ddr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/mach-imx/mx6/ddr.c +2 -2

index 52a9a25..39dbd2f 100644
@@ -908,7 +908,7 @@ void mx6sdl_dram_iocfg(unsigned width,
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
 #define MMDC1(entry, value) do {					  \
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())			  \
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())	  \
 		mmdc1->entry = value;					  \
 	} while (0)

@@ -1215,7 +1215,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 mem_speed = ddr3_cfg->mem_speed;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */

Signature · 1 line

2.7.4

Peng Fan

2018-01-02 00:53 UTC #1 lore raw

PATCH 1/1 mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL

Quoted 34 lines

-----Original Message-----
From: Fabio Estevam [mailto:festevam at gmail.com]
Sent: Tuesday, January 02, 2018 8:52 AM
To: sbabic at denx.de
Cc: u-boot at lists.denx.de; stefan at agner.ch; Peng Fan <[email protected]>; Fabio Estevam <[email protected]>
Subject: [PATCH] mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL
From: Fabio Estevam <[email protected]>
i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to access it.
Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/mach-imx/mx6/ddr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/mach-imx/mx6/ddr.c +1 -1
index 52a9a25..39dbd2f 100644
@@ -908,7 +908,7 @@ void mx6sdl_dram_iocfg(unsigned width,  #define
 MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
 #define MMDC1(entry, value) do {					  \
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())			  \
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())	  \
 		mmdc1->entry = value;					  \
 	} while (0)
 

arch/arm/mach-imx/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo · line 1220

Quoted 7 lines

arch/arm/mach-imx/mx6/ddr.c +1 -1

@@ -1215,7 +1215,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo
 *sysinfo,
 	u16 mem_speed = ddr3_cfg->mem_speed;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;

Reviewed-by Peng Fan <[email protected]>

Quoted 4 lines

arch/arm/mach-imx/mx6/ddr.c +0 -1
 	/* Limit mem_speed for MX6D/MX6Q */
--
2.7.4

Stefano Babic

2018-01-03 13:21 UTC #2 lore raw

PATCH 1/1 mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL

In reply to Fabio Estevam

Quoted 25 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to access it.

Signed-off-by Fabio Estevam <[email protected]>

---
 arch/arm/mach-imx/mx6/ddr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/mach-imx/mx6/ddr.c +1 -1

index 52a9a25..39dbd2f 100644
@@ -908,7 +908,7 @@ void mx6sdl_dram_iocfg(unsigned width,
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
 #define MMDC1(entry, value) do {					  \
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())			  \
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())	  \
 		mmdc1->entry = value;					  \
 	} while (0)

arch/arm/mach-imx/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1221

Quoted 8 lines

arch/arm/mach-imx/mx6/ddr.c +1 -1

@@ -1215,7 +1215,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 mem_speed = ddr3_cfg->mem_speed;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */

Reviewed-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2018-01-12 13:32 UTC #3 lore raw

PATCH 1/1 mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL

In reply to Fabio Estevam

Quoted 25 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to access it.

Signed-off-by Fabio Estevam <[email protected]>

---
 arch/arm/mach-imx/mx6/ddr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/mach-imx/mx6/ddr.c +1 -1

index 52a9a25..39dbd2f 100644
@@ -908,7 +908,7 @@ void mx6sdl_dram_iocfg(unsigned width,
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
 #define MMDC1(entry, value) do {					  \
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())			  \
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())	  \
 		mmdc1->entry = value;					  \
 	} while (0)

arch/arm/mach-imx/mx6/ddr.c void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, · line 1221

Quoted 8 lines

arch/arm/mach-imx/mx6/ddr.c +1 -1

@@ -1215,7 +1215,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 mem_speed = ddr3_cfg->mem_speed;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================