Patch "[Variant 2/Spectre-v2] arm/arm64: KVM: Add smccc accessors to PSCI code" has been added to the 4.15-stable tree
This is a note to let you know that I've just added the patch titled
[Variant 2/Spectre-v2] arm/arm64: KVM: Add smccc accessors to PSCI code
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-arm64-kvm-add-smccc-accessors-to-psci-code.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From foo@baz Tue Feb 13 17:25:10 CET 2018
From: Marc Zyngier <[email protected]>
Date: Tue, 6 Feb 2018 17:56:10 +0000
Subject: [Variant 2/Spectre-v2] arm/arm64: KVM: Add smccc accessors to PSCI code
From: Marc Zyngier <[email protected]>
Commit 84684fecd7ea upstream.
Instead of open coding the accesses to the various registers, let's add explicit SMCCC accessors.
--- virt/kvm/arm/psci.c | 52 ++++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 42 insertions(+), 10 deletions(-)
virt/kvm/arm/psci.c +42 -10
@@ -32,6 +32,38 @@#define AFFINITY_MASK (level) ~((0x1UL << ((level) * MPIDR_LEVEL_BITS)) - 1) +static u32 smccc_get_function (struct kvm_vcpu *vcpu) +{ +return vcpu_get_reg (vcpu,0 ); +} + +static unsigned long smccc_get_arg1 (struct kvm_vcpu *vcpu) +{ +return vcpu_get_reg (vcpu,1 ); +} + +static unsigned long smccc_get_arg2 (struct kvm_vcpu *vcpu) +{ +return vcpu_get_reg (vcpu,2 ); +} + +static unsigned long smccc_get_arg3 (struct kvm_vcpu *vcpu) +{ +return vcpu_get_reg (vcpu,3 ); +} + +static void smccc_set_retval (struct kvm_vcpu *vcpu, +unsigned long a0, +unsigned long a1, +unsigned long a2, +unsigned long a3) +{ +vcpu_set_reg (vcpu,0 , a0); +vcpu_set_reg (vcpu,1 , a1); +vcpu_set_reg (vcpu,2 , a2); +vcpu_set_reg (vcpu,3 , a3); +} +static unsigned long psci_affinity_mask (unsigned long affinity_level) {if (affinity_level <=3 )
@@ -77,7 +109,7 @@ static unsigned long kvm_psci_vcpu_on(stunsigned long context_id;phys_addr_t target_pc; - cpu_id =vcpu_get_reg (source_vcpu,1 ) &MPIDR_HWID_BITMASK ; + cpu_id =smccc_get_arg1 (source_vcpu) &MPIDR_HWID_BITMASK ;if (vcpu_mode_is_32bit (source_vcpu)) cpu_id &= ~((u32 )0 );
@@ -96,8 +128,8 @@ static unsigned long kvm_psci_vcpu_on(streturn PSCI_RET_INVALID_PARAMS ; } - target_pc =vcpu_get_reg (source_vcpu,2 ); - context_id =vcpu_get_reg (source_vcpu,3 ); + target_pc =smccc_get_arg2 (source_vcpu); + context_id =smccc_get_arg3 (source_vcpu);kvm_reset_vcpu (vcpu);
@@ -116,7 +148,7 @@ static unsigned long kvm_psci_vcpu_on(st* NOTE: We always update r0 (or x0) because for PSCI v0.1 * the general puspose registers are undefined upon CPU_ON. */ -vcpu_set_reg (vcpu,0 , context_id); +smccc_set_retval (vcpu, context_id,0 ,0 ,0 ); vcpu->arch.power_off = false;smp_mb ();/* Make sure the above is visible */
@@ -136,8 +168,8 @@ static unsigned long kvm_psci_vcpu_affinstruct kvm *kvm = vcpu->kvm;struct kvm_vcpu *tmp; - target_affinity =vcpu_get_reg (vcpu,1 ); - lowest_affinity_level =vcpu_get_reg (vcpu,2 ); + target_affinity =smccc_get_arg1 (vcpu); + lowest_affinity_level =smccc_get_arg2 (vcpu);/* Determine target affinity mask */ target_affinity_mask =psci_affinity_mask (lowest_affinity_level);
@@ -210,7 +242,7 @@ int kvm_psci_version(struct kvm_vcpu *vcstatic int kvm_psci_0_2_call (struct kvm_vcpu *vcpu) {struct kvm *kvm = vcpu->kvm; -unsigned long psci_fn =vcpu_get_reg (vcpu,0 ) & ~((u32 )0 ); +u32 psci_fn =smccc_get_function (vcpu);unsigned long val;int ret =1 ;
@@ -277,14 +309,14 @@ static int kvm_psci_0_2_call(struct kvm_break ; } -vcpu_set_reg (vcpu,0 , val); +smccc_set_retval (vcpu, val,0 ,0 ,0 );return ret; }static int kvm_psci_0_1_call (struct kvm_vcpu *vcpu) {struct kvm *kvm = vcpu->kvm; -unsigned long psci_fn =vcpu_get_reg (vcpu,0 ) & ~((u32 )0 ); +u32 psci_fn =smccc_get_function (vcpu);unsigned long val;switch (psci_fn) {
@@ -302,7 +334,7 @@ static int kvm_psci_0_1_call(struct kvm_break ; } -vcpu_set_reg (vcpu,0 , val); +smccc_set_retval (vcpu, val,0 ,0 ,0 );return 1 ; }
Patches currently in stable-queue which might be from [email protected] are
queue-4.15/arm-arm64-smccc-make-function-identifiers-an-unsigned-quantity.patch queue-4.15/arm64-move-bp-hardening-to-check_and_switch_context.patch queue-4.15/arm-arm64-kvm-advertise-smccc-v1.1.patch queue-4.15/arm64-move-post_ttbr_update_workaround-to-c-code.patch queue-4.15/firmware-psci-expose-psci-conduit.patch queue-4.15/arm64-force-kpti-to-be-disabled-on-cavium-thunderx.patch queue-4.15/arm64-entry-apply-bp-hardening-for-high-priority-synchronous-exceptions.patch queue-4.15/arm64-kpti-fix-the-interaction-between-asid-switching-and-software-pan.patch queue-4.15/firmware-psci-expose-smccc-version-through-psci_ops.patch queue-4.15/arm64-implement-branch-predictor-hardening-for-affected-cortex-a-cpus.patch queue-4.15/arm-arm64-kvm-add-psci_version-helper.patch queue-4.15/arm64-kill-psci_get_version-as-a-variant-2-workaround.patch queue-4.15/arm64-entry-apply-bp-hardening-for-suspicious-interrupts-from-el0.patch queue-4.15/arm64-capabilities-handle-duplicate-entries-for-a-capability.patch queue-4.15/arm64-add-arm_smccc_arch_workaround_1-bp-hardening-support.patch queue-4.15/arm-arm64-kvm-turn-kvm_psci_version-into-a-static-inline.patch queue-4.15/arm-arm64-kvm-implement-psci-1.0-support.patch queue-4.15/arm64-kvm-add-smccc_arch_workaround_1-fast-handling.patch queue-4.15/arm64-kvm-report-smccc_arch_workaround_1-bp-hardening-support.patch queue-4.15/arm-arm64-smccc-implement-smccc-v1.1-inline-primitive.patch queue-4.15/arm64-idmap-use-awx-flags-for-.idmap.text-.pushsection-directives.patch queue-4.15/arm64-kvm-make-psci_version-a-fast-path.patch queue-4.15/arm64-cpufeature-__this_cpu_has_cap-shouldn-t-stop-early.patch queue-4.15/arm64-kpti-add-enable-callback-to-remap-swapper-using-ng-mappings.patch queue-4.15/arm-arm64-kvm-consolidate-the-psci-include-files.patch queue-4.15/arm64-add-skeleton-to-harden-the-branch-predictor-against-aliasing-attacks.patch queue-4.15/arm-arm64-kvm-add-smccc-accessors-to-psci-code.patch queue-4.15/arm64-kvm-use-per-cpu-vector-when-bp-hardening-is-enabled.patch queue-4.15/arm64-kvm-increment-pc-after-handling-an-smc-trap.patch