Patch "[Variant 3/Meltdown] arm64: cpu_errata: Add Kryo to Falkor 1003 errata" has been added to the 4.15-stable tree
Subsystems (3)
This is a note to let you know that I've just added the patch titled
[Variant 3/Meltdown] arm64: cpu_errata: Add Kryo to Falkor 1003 errata
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-cpu_errata-add-kryo-to-falkor-1003-errata.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From foo@baz Tue Feb 13 17:25:10 CET 2018
From: Stephen Boyd <[email protected]>
Date: Wed, 13 Dec 2017 14:19:37 -0800
Subject: [Variant 3/Meltdown] arm64: cpu_errata: Add Kryo to Falkor 1003 errata
From: Stephen Boyd <[email protected]>
Commit bb48711800e6 upstream.
The Kryo CPUs are also affected by the Falkor 1003 errata, so we need to do the same workaround on Kryo CPUs. The MIDR is slightly more complicated here, where the PART number is not always the same when looking at all the bits from 15 to 4. Drop the lower 8 bits and just look at the top 4 to see if it's '2' and then consider those as Kryo CPUs. This covers all the combinations without having to list them all out.
Conflicts:
arch/arm64/include/asm/cputype.h
--- Documentation/arm64/silicon-errata.txt | 2 +- arch/arm64/include/asm/cputype.h | 2 ++ arch/arm64/kernel/cpu_errata.c | 21 +++++++++++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-)
Documentation/arm64/silicon-errata.txt +1 -1
@@ -72,7 +72,7 @@ stable kernels. | Hisilicon | Hip0{6,7} | #161010701 | N/A | | Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 | | | | | | -| Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | +| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | | Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 | | Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 |
arch/arm64/include/asm/cputype.h +2 -0
@@ -92,6 +92,7 @@#define QCOM_CPU_PART_FALKOR_V1 0x800#define QCOM_CPU_PART_FALKOR 0xC00 +#define QCOM_CPU_PART_KRYO 0x200#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
@@ -101,6 +102,7 @@#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) +#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)#ifndef __ASSEMBLY__
arch/arm64/kernel/cpu_errata.c +21 -0
@@ -30,6 +30,20 @@ is_affected_midr_range(const struct arm6 entry->midr_range_max); } +static bool __maybe_unused +is_kryo_midr (const struct arm64_cpu_capabilities *entry,int scope) +{ +u32 model; + +WARN_ON (scope !=SCOPE_LOCAL_CPU ||preemptible ()); + + model =read_cpuid_id (); + model &=MIDR_IMPLEMENTOR_MASK | (0xf00 <<MIDR_PARTNUM_SHIFT ) | +MIDR_ARCHITECTURE_MASK ; + +return model == entry->midr_model; +} +static bool has_mismatched_cache_line_size (const struct arm64_cpu_capabilities *entry,int scope)
@@ -169,6 +183,13 @@ const struct arm64_cpu_capabilities arm6 MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(0, 0)), }, + { + .desc = "Qualcomm Technologies Kryo erratum 1003", + .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, + .def_scope = SCOPE_LOCAL_CPU, + .midr_model = MIDR_QCOM_KRYO, + .matches = is_kryo_midr, + },#endif #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009 {
Patches currently in stable-queue which might be from [email protected] are
queue-4.15/arm64-cpu_errata-add-kryo-to-falkor-1003-errata.patch