perf/x86/intel: Fix: Use u64 for limit_period
Subsystems (2)
PATCH 1/1 perf/x86/intel: Fix: Use u64 for limit_period
From: Kan Liang <[email protected]>
The large fixed period could be truncated on Broadwell.
For example, perf record -e cycles -c 10000000000.
The fixed period is 0x2540BE400. But the period which finally applied is 0x540BE400.
Because the limit_period is unsigned, which is 32bit. The higher 32bit of the period will be truncated.
The issue is introduced since 'commit 294fe0f52a44 ("perf/x86/intel: Add INST_RETIRED.ALL workarounds")
Although the 'left' is s64, the value of 'left' must be positive when calling limit_period.bdw_limit_period() only modify the lowest 6 bits. It doesn't touch the higher 32bit.
So it's safe to use u64 to replace the unsigned.
--- arch/x86/events/intel/core.c | 2 +- arch/x86/events/perf_event.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
arch/x86/events/intel/core.c +1 -1
@@ -3222,7 +3222,7 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,* Therefore the effective (average) period matches the requested period, * despite coarser hardware granularity. */ -static unsigned bdw_limit_period (struct perf_event *event,unsigned left) +static u64 bdw_limit_period (struct perf_event *event,u64 left) {if ((event->hw.config &INTEL_ARCH_EVENT_MASK ) == X86_CONFIG(.event=0xc0, .umask=0x01)) {
arch/x86/events/perf_event.h +1 -1
@@ -561,7 +561,7 @@ struct x86_pmu {struct x86_pmu_quirk *quirks;int perfctr_second_write;bool late_ack; -unsigned (*limit_period)(struct perf_event *event,unsigned l); +u64 (*limit_period)(struct perf_event *event,u64 l);/* * sysfs attrs
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2.4.11
tip-bot for Kan Liang
merge bot[tip:perf/core] perf/x86/intel: Fix large period handling on Broadwell CPUs
perf/x86/intel: Fix large period handling on Broadwell CPUs
Commit-ID: f605cfca8c39ffa2b98c06d2b9f30ba64f1e54e3 Gitweb: https://git.kernel.org/tip/f605cfca8c39ffa2b98c06d2b9f30ba64f1e54e3 Author: Kan Liang <[email protected]> AuthorDate: Thu, 1 Mar 2018 12:54:54 -0500 Committer: Ingo Molnar <[email protected]> CommitDate: Fri, 9 Mar 2018 08:22:05 +0100
perf/x86/intel: Fix large period handling on Broadwell CPUs
Large fixed period values could be truncated on Broadwell, for example:
perf record -e cycles -c 10000000000
Here the fixed period is 0x2540BE400, but the period which finally applied is 0x540BE400 - which is wrong.
The reason is that x86_pmu::limit_period() uses an u32 parameter, so the high 32 bits of 'period' get truncated.
This bug was introduced in:
commit 294fe0f52a44 ("perf/x86/intel: Add INST_RETIRED.ALL workarounds")
It's safe to use u64 instead of u32:
- Although the 'left' is s64, the value of 'left' must be positive when calling limit_period().
- bdw_limit_period() only modifies the lowest 6 bits, it doesn't touch the higher 32 bits.
--- arch/x86/events/intel/core.c | 2 +- arch/x86/events/perf_event.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
arch/x86/events/intel/core.c +1 -1
@@ -3188,7 +3188,7 @@ glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,* Therefore the effective (average) period matches the requested period, * despite coarser hardware granularity. */ -static unsigned bdw_limit_period (struct perf_event *event,unsigned left) +static u64 bdw_limit_period (struct perf_event *event,u64 left) {if ((event->hw.config &INTEL_ARCH_EVENT_MASK ) == X86_CONFIG(.event=0xc0, .umask=0x01)) {
arch/x86/events/perf_event.h +1 -1
@@ -557,7 +557,7 @@ struct x86_pmu {struct x86_pmu_quirk *quirks;int perfctr_second_write;bool late_ack; -unsigned (*limit_period)(struct perf_event *event,unsigned l); +u64 (*limit_period)(struct perf_event *event,u64 l);/* * sysfs attrs