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Patch "drm/amdgpu: used cached pcie gen info for SI (v2)" has been added to the 4.15-stable tree

PATCH [email protected] 1 participant 1 message Mar 12, 2018

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This is a note to let you know that I've just added the patch titled

drm/amdgpu: used cached pcie gen info for SI (v2)

to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
drm-amdgpu-used-cached-pcie-gen-info-for-si-v2.patch
and it can be found in the queue-4.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From 05656e5e4917a08296300dc0530aed1539202c25 Mon Sep 17 00:00:00 2001

From: Alex Deucher <[email protected]>
Date: Mon, 26 Feb 2018 11:05:10 -0500
Subject: drm/amdgpu: used cached pcie gen info for SI (v2)
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From: Alex Deucher <[email protected]>

commit 05656e5e4917a08296300dc0530aed1539202c25 upstream.

Rather than querying it every time we need it. Also fixes a crash in VM pass through if there is no root bridge because the cached value fetch already checks this properly.

v2: fix includes

---
 drivers/gpu/drm/amd/amdgpu/si.c     |   22 +++++++--------
 drivers/gpu/drm/amd/amdgpu/si_dpm.c |   50 +++++++++---------------------------
 2 files changed, 23 insertions(+), 49 deletions(-)
drivers/gpu/drm/amd/amdgpu/si.c +10 -12
@@ -31,6 +31,7 @@
 #include "amdgpu_uvd.h"
 #include "amdgpu_vce.h"
 #include "atom.h"
+#include "amd_pcie.h"
 #include "amdgpu_powerplay.h"
 #include "sid.h"
 #include "si_ih.h"
@@ -1461,8 +1462,8 @@ static void si_pcie_gen3_enable(struct a
 {
 	struct pci_dev *root = adev->pdev->bus->self;
 	int bridge_pos, gpu_pos;
-	u32 speed_cntl, mask, current_data_rate;
-	int ret, i;
+	u32 speed_cntl, current_data_rate;
+	int i;
 	u16 tmp16;
 
 	if (pci_is_root_bus(adev->pdev->bus))
@@ -1474,23 +1475,20 @@ static void si_pcie_gen3_enable(struct a
 	if (adev->flags & AMD_IS_APU)
 		return;
 
-	ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
-	if (ret != 0)
-		return;
-
-	if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
+	if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+					CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 		return;
 
 	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
 	current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
 		LC_CURRENT_DATA_RATE_SHIFT;
-	if (mask & DRM_PCIE_SPEED_80) {
+	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
 		if (current_data_rate == 2) {
 			DRM_INFO("PCIE gen 3 link speeds already enabled\n");
 			return;
 		}
 		DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
-	} else if (mask & DRM_PCIE_SPEED_50) {
+	} else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
 		if (current_data_rate == 1) {
 			DRM_INFO("PCIE gen 2 link speeds already enabled\n");
 			return;
@@ -1506,7 +1504,7 @@ static void si_pcie_gen3_enable(struct a
 	if (!gpu_pos)
 		return;
 
-	if (mask & DRM_PCIE_SPEED_80) {
+	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
 		if (current_data_rate != 2) {
 			u16 bridge_cfg, gpu_cfg;
 			u16 bridge_cfg2, gpu_cfg2;
@@ -1589,9 +1587,9 @@ static void si_pcie_gen3_enable(struct a
 
 	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
 	tmp16 &= ~0xf;
-	if (mask & DRM_PCIE_SPEED_80)
+	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 		tmp16 |= 3;
-	else if (mask & DRM_PCIE_SPEED_50)
+	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 		tmp16 |= 2;
 	else
 		tmp16 |= 1;
drivers/gpu/drm/amd/amdgpu/si_dpm.c +13 -37

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Patches currently in stable-queue which might be from [email protected] are

queue-4.15/drm-amdgpu-notify-sbios-device-ready-before-send-request.patch queue-4.15/workqueue-allow-retrieval-of-current-task-s-work-struct.patch queue-4.15/drm-amd-display-default-hdmi6g-support-to-true.-log-vbios-table-error.patch queue-4.15/drm-amd-powerplay-vega10-allow-mclk-switching-with-no-displays.patch queue-4.15/drm-radeon-fix-kv-harvesting.patch queue-4.15/drm-radeon-fix-deadlock-on-runtime-suspend.patch queue-4.15/drm-amdgpu-correct-max-uvd-handles.patch queue-4.15/drm-amd-powerplay-smu7-allow-mclk-switching-with-no-displays.patch queue-4.15/drm-amd-display-check-for-ipp-before-calling-cursor-operations.patch queue-4.15/drm-amdgpu-fix-deadlock-on-runtime-suspend.patch queue-4.15/drm-amd-powerplay-fix-power-over-limit-on-fiji.patch queue-4.15/drm-allow-determining-if-current-task-is-output-poll-worker.patch queue-4.15/drm-amdgpu-used-cached-pcie-gen-info-for-si-v2.patch queue-4.15/revert-drm-radeon-pm-autoswitch-power-state-when-in-balanced-mode.patch queue-4.15/drm-amdgpu-fix-kv-harvesting.patch queue-4.15/drm-amdgpu-always-save-uvd-vcpu_bo-in-vm-mode.patch queue-4.15/drm-radeon-insist-on-32-bit-dma-for-cedar-on-ppc64-ppc64le.patch