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Patch "drivers: net: xgene: Fix hardware checksum setting" has been added to the 4.9-stable tree

PATCH [email protected] 1 participant 1 message Mar 18, 2018

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This is a note to let you know that I've just added the patch titled

drivers: net: xgene: Fix hardware checksum setting

to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
drivers-net-xgene-fix-hardware-checksum-setting.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From foo@baz Sun Mar 18 16:55:33 CET 2018

From: Quan Nguyen <[email protected]>
Date: Wed, 15 Mar 2017 13:27:16 -0700
Subject: drivers: net: xgene: Fix hardware checksum setting

From: Quan Nguyen <[email protected]>

[ Upstream commit e026e700d940a1ea3d3bc84d92ac668b1f015462 ]

This patch fixes the hardware checksum settings by properly program the classifier. Otherwise, packet may be received with checksum error on X-Gene1 SoC.

---
 drivers/net/ethernet/apm/xgene/xgene_enet_hw.c |    1 +
 drivers/net/ethernet/apm/xgene/xgene_enet_hw.h |    1 +
 2 files changed, 2 insertions(+)
drivers/net/ethernet/apm/xgene/xgene_enet_hw.c +1 -0
@@ -560,6 +560,7 @@ static void xgene_enet_cle_bypass(struct
 	xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
 	cb |= CFG_CLE_BYPASS_EN0;
 	CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
+	CFG_CLE_IP_HDR_LEN_SET(&cb, 0);
 	xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
 
 	xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
drivers/net/ethernet/apm/xgene/xgene_enet_hw.h +1 -0
@@ -163,6 +163,7 @@ enum xgene_enet_rm {
 #define CFG_RXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 26, 3)
 
 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val)	xgene_set_bits(dst, val, 16, 2)
+#define CFG_CLE_IP_HDR_LEN_SET(dst, val)	xgene_set_bits(dst, val, 8, 5)
 #define CFG_CLE_DSTQID0_SET(dst, val)		xgene_set_bits(dst, val, 0, 12)
 #define CFG_CLE_FPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 16, 4)
 #define CFG_MACMODE_SET(dst, val)		xgene_set_bits(dst, val, 18, 2)

Patches currently in stable-queue which might be from [email protected] are

queue-4.9/drivers-net-xgene-fix-wrong-logical-operation.patch queue-4.9/drivers-net-xgene-fix-hardware-checksum-setting.patch queue-4.9/drivers-net-phy-xgene-fix-mdio-write.patch