Patch "MIPS: lantiq: Fix Danube USB clock" has been added to the 4.15-stable tree

This is a note to let you know that I've just added the patch titled

MIPS: lantiq: Fix Danube USB clock

to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
mips-lantiq-fix-danube-usb-clock.patch
and it can be found in the queue-4.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Mathias Kresin <[email protected]>
Date: Fri, 16 Mar 2018 21:27:28 +0100
Subject: MIPS: lantiq: Fix Danube USB clock

From: Mathias Kresin <[email protected]>

commit 214cbc14734958fe533916fdb4194f5983ad4bc4 upstream.

On Danube the USB0 controller registers are at 1e101000 and the USB0 PHY register is at 1f203018 similar to all other lantiq SoCs. Activate the USB controller gating clock thorough the USB controller driver and not the PHY.

This fixes a problem introduced in a previous commit.

Patchwork: https://patchwork.linux-mips.org/patch/18816/

---
 arch/mips/lantiq/xway/sysctrl.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

@@ -560,7 +560,7 @@ void __init ltq_soc_init(void)
 	} else {
 		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
 				ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
-		clkdev_add_pmu("1f203018.usb2-phy", "ctrl", 1, 0, PMU_USB0);
+		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
 		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
 		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
 		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);

Patches currently in stable-queue which might be from [email protected] are

queue-4.15/mips-lantiq-ase-enable-mfd_syscon.patch queue-4.15/mips-lantiq-enable-ahb-bus-for-usb.patch queue-4.15/mips-lantiq-fix-danube-usb-clock.patch