Patch "x86/microcode/intel: Check microcode revision before updating sibling threads" has been added to the 4.15-stable tree

This is a note to let you know that I've just added the patch titled

x86/microcode/intel: Check microcode revision before updating sibling threads

to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
and it can be found in the queue-4.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Ashok Raj <[email protected]>
Date: Wed, 28 Feb 2018 11:28:41 +0100
Subject: x86/microcode/intel: Check microcode revision before updating sibling threads

From: Ashok Raj <[email protected]>

commit c182d2b7d0ca48e0d6ff16f7d883161238c447ed upstream.

After updating microcode on one of the threads of a core, the other thread sibling automatically gets the update since the microcode resources on a hyperthreaded core are shared between the two threads.

Check the microcode revision on the CPU before performing a microcode update and thus save us the WRMSR 0x79 because it is a particularly expensive operation.

[ Borislav: Massage changelog and coding style. ]

---
 arch/x86/kernel/cpu/microcode/intel.c |   27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

@@ -589,6 +589,17 @@ static int apply_microcode_early(struct
 	if (!mc)
 		return 0;
 
+	/*
+	 * Save us the MSR write below - which is a particular expensive
+	 * operation - when the other hyperthread has updated the microcode
+	 * already.
+	 */
+	rev = intel_get_microcode_revision();
+	if (rev >= mc->hdr.rev) {
+		uci->cpu_sig.rev = rev;
+		return UCODE_OK;
+	}
+
 	/* write microcode via MSR 0x79 */
 	native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 

@@ -776,7 +787,7 @@ static enum ucode_state apply_microcode_
 {
 	struct microcode_intel *mc;
 	struct ucode_cpu_info *uci;
-	struct cpuinfo_x86 *c;
+	struct cpuinfo_x86 *c = &cpu_data(cpu);
 	static int prev_rev;
 	u32 rev;
 

@@ -793,6 +804,18 @@ static enum ucode_state apply_microcode_
 			return UCODE_NFOUND;
 	}
 
+	/*
+	 * Save us the MSR write below - which is a particular expensive
+	 * operation - when the other hyperthread has updated the microcode
+	 * already.
+	 */
+	rev = intel_get_microcode_revision();
+	if (rev >= mc->hdr.rev) {
+		uci->cpu_sig.rev = rev;
+		c->microcode = rev;
+		return UCODE_OK;
+	}
+
 	/* write microcode via MSR 0x79 */
 	wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
 

@@ -813,8 +836,6 @@ static enum ucode_state apply_microcode_
 		prev_rev = rev;
 	}
 
-	c = &cpu_data(cpu);
-
 	uci->cpu_sig.rev = rev;
 	c->microcode = rev;
 

Patches currently in stable-queue which might be from [email protected] are

queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch