x86: ivybridge: cougarcanyon2: Various enhancements

This fixes the following compiler warning:

"warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]"

Signed-off-by Bin Meng <[email protected]>

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 drivers/usb/host/xhci-pci.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Quoted 5 lines · Bin Meng

This fixes the following compiler warning:

"warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]"

Quoted 5 lines

Signed-off-by Bin Meng <[email protected]>

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 drivers/usb/host/xhci-pci.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Reviewed-by Simon Glass <[email protected]>

The Panther Point chipset connected to Ivybridge has xHC integrated, imply it.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/cpu/ivybridge/Kconfig | 1 +
 1 file changed, 1 insertion(+)

Quoted 3 lines · Bin Meng

The Panther Point chipset connected to Ivybridge has xHC integrated, imply it.

Quoted 6 lines

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/cpu/ivybridge/Kconfig | 1 +
 1 file changed, 1 insertion(+)

Reviewed-by Simon Glass <[email protected]>

It turns out that like Braswell, Intel FSP for IvyBridge requires SPI controller settings to be locked down, as the U-Boot ICH SPI driver fails with the following message on Cougar Canyon 2 board:

"ICH SPI: Opcode 9f not found"

Update the SPI node property to indicate this fact.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/dts/cougarcanyon2.dts | 2 ++
 1 file changed, 2 insertions(+)

Quoted 8 lines · Bin Meng

It turns out that like Braswell, Intel FSP for IvyBridge requires SPI controller settings to be locked down, as the U-Boot ICH SPI driver fails with the following message on Cougar Canyon 2 board:

"ICH SPI: Opcode 9f not found"

Update the SPI node property to indicate this fact.

Quoted 5 lines

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/dts/cougarcanyon2.dts | 2 ++
 1 file changed, 2 insertions(+)

Reviewed-by Simon Glass <[email protected]>

As README.x86 already mentions, there are two SPI flashes mounted on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively. SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores the actual BIOS image which is U-Boot. Building a single image with both ME firmware and U-Boot does not make sense.

This also describes the exact flash location where the u-boot.rom should be programmed in the documentation.

Signed-off-by Bin Meng <[email protected]>

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 configs/cougarcanyon2_defconfig | 1 +
 doc/README.x86                  | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

Quoted 9 lines · Bin Meng

As README.x86 already mentions, there are two SPI flashes mounted on Intel Cougar Canyon 2 board, called SPI-0 and SPI-1 respectively. SPI-0 stores the flash descriptor and the ME firmware. SPI-1 stores the actual BIOS image which is U-Boot. Building a single image with both ME firmware and U-Boot does not make sense.

This also describes the exact flash location where the u-boot.rom should be programmed in the documentation.

Quoted 6 lines

Signed-off-by Bin Meng <[email protected]>

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 configs/cougarcanyon2_defconfig | 1 +
 doc/README.x86                  | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

Reviewed-by Simon Glass <[email protected]>

At present this 206ax cpu driver is only built when FSP is not used. This updates the Makefile to enable the build for both cases.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/cpu/ivybridge/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Quoted 8 lines · Bin Meng

At present this 206ax cpu driver is only built when FSP is not used. This updates the Makefile to enable the build for both cases.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/cpu/ivybridge/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by Simon Glass <[email protected]>

This is not used anywhere. Clean this up.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/cpu/intel_common/mrc.c      |  5 -----
 arch/x86/cpu/ivybridge/model_206ax.c | 15 ---------------
 scripts/config_whitelist.txt         |  1 -
 3 files changed, 21 deletions(-)

Quoted 5 lines · Bin Meng

This is not used anywhere. Clean this up.

Signed-off-by Bin Meng <[email protected]>

---

Quoted 4 lines

 arch/x86/cpu/intel_common/mrc.c      |  5 -----
 arch/x86/cpu/ivybridge/model_206ax.c | 15 ---------------
 scripts/config_whitelist.txt         |  1 -
 3 files changed, 21 deletions(-)

Reviewed-by Simon Glass <[email protected]>

The 206ax cpu driver does not require pre-relocation flag to work.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/dts/chromebook_link.dts | 5 -----
 1 file changed, 5 deletions(-)

Quoted 8 lines · Bin Meng

The 206ax cpu driver does not require pre-relocation flag to work.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/dts/chromebook_link.dts | 5 -----
 1 file changed, 5 deletions(-)

Reviewed-by Simon Glass <[email protected]>

This enables the 206ax cpu driver on Intel Cougar Canyon 2 board, so that SMP can be supported too.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/dts/cougarcanyon2.dts  | 33 +++++++++++++++++++++++++++++++++
 configs/cougarcanyon2_defconfig |  3 +++
 2 files changed, 36 insertions(+)

Quoted 6 lines · Bin Meng

This enables the 206ax cpu driver on Intel Cougar Canyon 2 board, so that SMP can be supported too.

Signed-off-by Bin Meng <[email protected]>

---

Quoted 4 lines

 arch/x86/dts/cougarcanyon2.dts  | 33 +++++++++++++++++++++++++++++++++
 configs/cougarcanyon2_defconfig |  3 +++
 2 files changed, 36 insertions(+)

Reviewed-by Simon Glass <[email protected]>

At present there are 3 irq router drivers. One is the common one and the other two are chipset specific for queensbay and quark. However these are really the same drivers as the core logic is the same. The two chipset specific drivers configure some registers that are outside the irq router block which should really be part of the chipset initialization.

Now we remove these specific drivers and make all x86 boards use the common one.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/cpu/irq.c              |  7 +----
 arch/x86/cpu/quark/Makefile     |  2 +-
 arch/x86/cpu/quark/irq.c        | 48 -------------------------------
 arch/x86/cpu/quark/quark.c      | 26 +++++++++++++++++
 arch/x86/cpu/queensbay/Makefile |  2 +-
 arch/x86/cpu/queensbay/irq.c    | 64 -----------------------------------------
 arch/x86/cpu/queensbay/tnc.c    | 39 +++++++++++++++++++++++++
 arch/x86/dts/crownbay.dts       |  2 +-
 arch/x86/dts/galileo.dts        |  2 +-
 arch/x86/include/asm/irq.h      |  7 -----
 10 files changed, 70 insertions(+), 129 deletions(-)
 delete mode 100644 arch/x86/cpu/quark/irq.c
 delete mode 100644 arch/x86/cpu/queensbay/irq.c

Quoted 13 lines · Bin Meng

At present there are 3 irq router drivers. One is the common one and the other two are chipset specific for queensbay and quark. However these are really the same drivers as the core logic is the same. The two chipset specific drivers configure some registers that are outside the irq router block which should really be part of the chipset initialization.

Now we remove these specific drivers and make all x86 boards use the common one.

Signed-off-by Bin Meng <[email protected]>

---

Quoted 13 lines

 arch/x86/cpu/irq.c              |  7 +----
 arch/x86/cpu/quark/Makefile     |  2 +-
 arch/x86/cpu/quark/irq.c        | 48 -------------------------------
 arch/x86/cpu/quark/quark.c      | 26 +++++++++++++++++
 arch/x86/cpu/queensbay/Makefile |  2 +-
 arch/x86/cpu/queensbay/irq.c    | 64 -----------------------------------------
 arch/x86/cpu/queensbay/tnc.c    | 39 +++++++++++++++++++++++++
 arch/x86/dts/crownbay.dts       |  2 +-
 arch/x86/dts/galileo.dts        |  2 +-
 arch/x86/include/asm/irq.h      |  7 -----
 10 files changed, 70 insertions(+), 129 deletions(-)
 delete mode 100644 arch/x86/cpu/quark/irq.c
 delete mode 100644 arch/x86/cpu/queensbay/irq.c

Reviewed-by Simon Glass <[email protected]>

LINK_V2N and LINK_N2V are currently defines, so they cannot handle complex logics. Change to inline functions for future extension.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/cpu/irq.c         | 18 +++++++++++-------
 arch/x86/include/asm/irq.h | 26 +++++++++++++++++++++++---
 2 files changed, 34 insertions(+), 10 deletions(-)

Quoted 6 lines · Bin Meng

LINK_V2N and LINK_N2V are currently defines, so they cannot handle complex logics. Change to inline functions for future extension.

Signed-off-by Bin Meng <[email protected]>

---

Quoted 4 lines

 arch/x86/cpu/irq.c         | 18 +++++++++++-------
 arch/x86/include/asm/irq.h | 26 +++++++++++++++++++++++---
 2 files changed, 34 insertions(+), 10 deletions(-)

Reviewed-by Simon Glass <[email protected]>

Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume consecutive PIRQ routing control registers. But this is not always the case on some platforms. Introduce a Kconfig option for this and adjust the irq router driver to be able to use platform-specific converting logic.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/Kconfig           | 9 +++++++++
 arch/x86/cpu/irq.c         | 3 +++
 arch/x86/include/asm/irq.h | 2 ++
 3 files changed, 14 insertions(+)

Add Panther Point chipset interrupt pin/PIRQ information, and enable the generation of PIRQ routing table and MP table.

Signed-off-by Bin Meng <[email protected]>

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 arch/x86/dts/cougarcanyon2.dts  | 36 ++++++++++++++++++++++++++++++++++++
 configs/cougarcanyon2_defconfig |  2 ++
 2 files changed, 38 insertions(+)