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iio: accel: adxl345: add calibration offset and sampling frequency support

PATCH Superseded Akinobu Mita 2 participants 6 messages Jun 21, 2018 – Jun 24, 2018

Subsystems (2)
IIO Analog Devices IIO drivers

v3 of 6 Superseded Latest is v6 →

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Akinobu Mita

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#0 lore raw

v3 cover iio: accel: adxl345: add calibration offset and sampling frequency support

This patchset adds calibration offset and sampling frequency support for adxl345 driver with some preparatory changes.

* v3 (Suggested by Andy Shevchenko)
- Define ADXL345_REG_DATA_AXIS(si) for cleaner register access
- Define ADXL345_REG_OSF_AXIS(si) for cleaner register access
- Calculate sampling frequency at runtime instead of having constant table

* v2
- Adjust the value for the calibbias to make the same scale as the _raw measurement, and remove misused calibscale.

Akinobu Mita (4):
iio: accel: adxl345: add link to datasheet
iio: accel: adxl345: use scan_index for accessing accel registers
iio: accel: adxl345: add calibration offset support
iio: accel: adxl345: add sampling frequency support

 drivers/iio/accel/adxl345_core.c | 128 +++++++++++++++++++++++++++++++++++----
 1 file changed, 117 insertions(+), 11 deletions(-)
Cc Eva Rachel Retuya <[email protected]>
Cc Andy Shevchenko <[email protected]>
Cc Jonathan Cameron <[email protected]>
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2.7.4
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#1 lore raw

PATCH v3 1/4 iio: accel: adxl345: add link to datasheet

Add a link to the ADXL345 datasheet

Cc Eva Rachel Retuya <[email protected]>
Cc Andy Shevchenko <[email protected]>
Cc Jonathan Cameron <[email protected]>
Signed-off-by Akinobu Mita <[email protected]>

---
* v3
- No changes from v2

 drivers/iio/accel/adxl345_core.c | 2 ++
 1 file changed, 2 insertions(+)
drivers/iio/accel/adxl345_core.c +2 -0
index 7251d0e..8e0d56b 100644
@@ -6,6 +6,8 @@
  * This file is subject to the terms and conditions of version 2 of
  * the GNU General Public License. See the file COPYING in the main
  * directory of this archive for more details.
+ *
+ * Datasheet: http://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf
  */
 
 #include <linux/module.h>
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2.7.4
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#2 lore raw

PATCH v3 2/4 iio: accel: adxl345: use scan_index for accessing accel registers

In reply to Akinobu Mita

Currently the address field in iio_chan_spec is filled with an accel data register address for the corresponding axis.

In preparation for adding calibration offset support, this makes use of scan_index field to access accel data registers instead of using address field. This change makes it easier to access both accel registers and calibration offset registers with fewer lines of code as these are located in X-axis, Y-axis, Z-axis order.

Cc Eva Rachel Retuya <[email protected]>
Cc Andy Shevchenko <[email protected]>
Cc Jonathan Cameron <[email protected]>
Signed-off-by Akinobu Mita <[email protected]>

---
* v3
- Define ADXL345_REG_DATA_AXIS(si) for cleaner register access

 drivers/iio/accel/adxl345_core.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)
drivers/iio/accel/adxl345_core.c +12 -9
index 8e0d56b..ef641db 100644
@@ -23,6 +23,8 @@
 #define ADXL345_REG_DATAX0		0x32
 #define ADXL345_REG_DATAY0		0x34
 #define ADXL345_REG_DATAZ0		0x36
+#define ADXL345_REG_DATA_AXIS(si)	\
+	(ADXL345_REG_DATAX0 + (si) * sizeof(__le16))
 
 #define ADXL345_POWER_CTL_MEASURE	BIT(3)
 #define ADXL345_POWER_CTL_STANDBY	0x00

@@ -49,19 +51,19 @@ struct adxl345_data {
 	u8 data_range;
 };
 
-#define ADXL345_CHANNEL(reg, axis) {					\
+#define ADXL345_CHANNEL(si, axis) {					\
 	.type = IIO_ACCEL,						\
 	.modified = 1,							\
 	.channel2 = IIO_MOD_##axis,					\
-	.address = reg,							\
 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\
+	.scan_index = si,						\
 }
 
 static const struct iio_chan_spec adxl345_channels[] = {
-	ADXL345_CHANNEL(ADXL345_REG_DATAX0, X),
-	ADXL345_CHANNEL(ADXL345_REG_DATAY0, Y),
-	ADXL345_CHANNEL(ADXL345_REG_DATAZ0, Z),
+	ADXL345_CHANNEL(0, X),
+	ADXL345_CHANNEL(1, Y),
+	ADXL345_CHANNEL(2, Z),
 };
 
 static int adxl345_read_raw(struct iio_dev *indio_dev,

@@ -69,7 +71,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
 			    int *val, int *val2, long mask)
 {
 	struct adxl345_data *data = iio_priv(indio_dev);
-	__le16 regval;
+	__le16 accel;
 	int ret;
 
 	switch (mask) {

@@ -79,12 +81,13 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
 		 * ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte
 		 * and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte
 		 */
-		ret = regmap_bulk_read(data->regmap, chan->address, &regval,
-				       sizeof(regval));
+		ret = regmap_bulk_read(data->regmap,
+				       ADXL345_REG_DATA_AXIS(chan->scan_index),
+				       &accel, sizeof(accel));
 		if (ret < 0)
 			return ret;
 
-		*val = sign_extend32(le16_to_cpu(regval), 12);
+		*val = sign_extend32(le16_to_cpu(accel), 12);
 		return IIO_VAL_INT;
 	case IIO_CHAN_INFO_SCALE:
 		*val = 0;
Signature · 1 line
2.7.4
maintainer
#3 lore raw

Re: [PATCH v3 2/4] iio: accel: adxl345: use scan_index for accessing accel registers

Quoted 9 lines · On Fri, 22 Jun 2018 00:39:06 +0900 Akinobu Mita <[email protected]> wrote:

Currently the address field in iio_chan_spec is filled with an accel data register address for the corresponding axis.

In preparation for adding calibration offset support, this makes use of scan_index field to access accel data registers instead of using address field. This change makes it easier to access both accel registers and calibration offset registers with fewer lines of code as these are located in X-axis, Y-axis, Z-axis order.

Quoted 4 lines
Cc Eva Rachel Retuya <[email protected]>
Cc Andy Shevchenko <[email protected]>
Cc Jonathan Cameron <[email protected]>
Signed-off-by Akinobu Mita <[email protected]>

Sorry I didn't get back to you earlier, but see comment in my review for the previous version. I'd rather this wasn't done with scan_index on the basis that it's not what that field is really for. If we were already using that field for it's normal purpose (ordering in the buffered interface) then I'd be fine with also using it for this. The other way around isn't true..

Jonathan

Quoted 71 lines

---
* v3
- Define ADXL345_REG_DATA_AXIS(si) for cleaner register access

 drivers/iio/accel/adxl345_core.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)
drivers/iio/accel/adxl345_core.c +12 -9
index 8e0d56b..ef641db 100644
@@ -23,6 +23,8 @@
 #define ADXL345_REG_DATAX0		0x32
 #define ADXL345_REG_DATAY0		0x34
 #define ADXL345_REG_DATAZ0		0x36
+#define ADXL345_REG_DATA_AXIS(si)	\
+	(ADXL345_REG_DATAX0 + (si) * sizeof(__le16))
 
 #define ADXL345_POWER_CTL_MEASURE	BIT(3)
 #define ADXL345_POWER_CTL_STANDBY	0x00

@@ -49,19 +51,19 @@ struct adxl345_data {
 	u8 data_range;
 };
 
-#define ADXL345_CHANNEL(reg, axis) {					\
+#define ADXL345_CHANNEL(si, axis) {					\
 	.type = IIO_ACCEL,						\
 	.modified = 1,							\
 	.channel2 = IIO_MOD_##axis,					\
-	.address = reg,							\
 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\
+	.scan_index = si,						\
 }
 
 static const struct iio_chan_spec adxl345_channels[] = {
-	ADXL345_CHANNEL(ADXL345_REG_DATAX0, X),
-	ADXL345_CHANNEL(ADXL345_REG_DATAY0, Y),
-	ADXL345_CHANNEL(ADXL345_REG_DATAZ0, Z),
+	ADXL345_CHANNEL(0, X),
+	ADXL345_CHANNEL(1, Y),
+	ADXL345_CHANNEL(2, Z),
 };
 
 static int adxl345_read_raw(struct iio_dev *indio_dev,

@@ -69,7 +71,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
 			    int *val, int *val2, long mask)
 {
 	struct adxl345_data *data = iio_priv(indio_dev);
-	__le16 regval;
+	__le16 accel;
 	int ret;
 
 	switch (mask) {

@@ -79,12 +81,13 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
 		 * ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte
 		 * and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte
 		 */
-		ret = regmap_bulk_read(data->regmap, chan->address, &regval,
-				       sizeof(regval));
+		ret = regmap_bulk_read(data->regmap,
+				       ADXL345_REG_DATA_AXIS(chan->scan_index),
+				       &accel, sizeof(accel));
 		if (ret < 0)
 			return ret;
 
-		*val = sign_extend32(le16_to_cpu(regval), 12);
+		*val = sign_extend32(le16_to_cpu(accel), 12);
 		return IIO_VAL_INT;
 	case IIO_CHAN_INFO_SCALE:
 		*val = 0;
author
#4 lore raw

PATCH v3 3/4 iio: accel: adxl345: add calibration offset support

In reply to Akinobu Mita

The ADXL345 provides the offset adjustment registers for each axis. This adds the iio channel information for the calibraion offsets with that feature.

Cc Eva Rachel Retuya <[email protected]>
Cc Andy Shevchenko <[email protected]>
Cc Jonathan Cameron <[email protected]>
Signed-off-by Akinobu Mita <[email protected]>

---
* v3
- Define ADXL345_REG_OSF_AXIS(si) for cleaner register access

 drivers/iio/accel/adxl345_core.c | 42 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 41 insertions(+), 1 deletion(-)
drivers/iio/accel/adxl345_core.c +41 -1
index ef641db..d109ca5 100644
@@ -18,6 +18,10 @@
 #include "adxl345.h"
 
 #define ADXL345_REG_DEVID		0x00
+#define ADXL345_REG_OFSX		0x1e
+#define ADXL345_REG_OFSY		0x1f
+#define ADXL345_REG_OFSZ		0x20
+#define ADXL345_REG_OFS_AXIS(si)	(ADXL345_REG_OFSX + (si))
 #define ADXL345_REG_POWER_CTL		0x2D
 #define ADXL345_REG_DATA_FORMAT		0x31
 #define ADXL345_REG_DATAX0		0x32

@@ -55,7 +59,8 @@ struct adxl345_data {
 	.type = IIO_ACCEL,						\
 	.modified = 1,							\
 	.channel2 = IIO_MOD_##axis,					\
-	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
+	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
+		BIT(IIO_CHAN_INFO_CALIBBIAS),				\
 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\
 	.scan_index = si,						\
 }

@@ -72,6 +77,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
 {
 	struct adxl345_data *data = iio_priv(indio_dev);
 	__le16 accel;
+	unsigned int regval;
 	int ret;
 
 	switch (mask) {

@@ -94,6 +100,39 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
 		*val2 = adxl345_uscale;
 
 		return IIO_VAL_INT_PLUS_MICRO;
+	case IIO_CHAN_INFO_CALIBBIAS:
+		ret = regmap_read(data->regmap,
+				  ADXL345_REG_OFS_AXIS(chan->scan_index),
+				  &regval);
+		if (ret < 0)
+			return ret;
+		/*
+		 * 8-bit resolution at +/- 2g, that is 4x accel data scale
+		 * factor
+		 */
+		*val = sign_extend32(regval, 7) * 4;
+
+		return IIO_VAL_INT;
+	}
+
+	return -EINVAL;
+}
+
+static int adxl345_write_raw(struct iio_dev *indio_dev,
+			    struct iio_chan_spec const *chan,
+			    int val, int val2, long mask)
+{
+	struct adxl345_data *data = iio_priv(indio_dev);
+
+	switch (mask) {
+	case IIO_CHAN_INFO_CALIBBIAS:
+		/*
+		 * 8-bit resolution at +/- 2g, that is 4x accel data scale
+		 * factor
+		 */
+		return regmap_write(data->regmap,
+				    ADXL345_REG_OFSX + chan->scan_index,
+				    val / 4);
 	}
 
 	return -EINVAL;

@@ -101,6 +140,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
 
 static const struct iio_info adxl345_info = {
 	.read_raw	= adxl345_read_raw,
+	.write_raw	= adxl345_write_raw,
 };
 
 int adxl345_core_probe(struct device *dev, struct regmap *regmap,
Signature · 1 line
2.7.4
author
#5 lore raw

PATCH v3 4/4 iio: accel: adxl345: add sampling frequency support

In reply to Akinobu Mita

The ADXL345 provides selectable output data rate. This adds the iio channel information for the sampling frequency with that feature.

Cc Eva Rachel Retuya <[email protected]>
Cc Andy Shevchenko <[email protected]>
Cc Jonathan Cameron <[email protected]>
Signed-off-by Akinobu Mita <[email protected]>

---
* v3
- Calculate sampling frequency at runtime instead of having constant table

 drivers/iio/accel/adxl345_core.c | 63 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 62 insertions(+), 1 deletion(-)
drivers/iio/accel/adxl345_core.c +62 -1
index d109ca5..460b3c9 100644
@@ -14,6 +14,7 @@
 #include <linux/regmap.h>
 
 #include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
 
 #include "adxl345.h"
 

@@ -22,6 +23,7 @@
 #define ADXL345_REG_OFSY		0x1f
 #define ADXL345_REG_OFSZ		0x20
 #define ADXL345_REG_OFS_AXIS(si)	(ADXL345_REG_OFSX + (si))
+#define ADXL345_REG_BW_RATE		0x2C
 #define ADXL345_REG_POWER_CTL		0x2D
 #define ADXL345_REG_DATA_FORMAT		0x31
 #define ADXL345_REG_DATAX0		0x32

@@ -30,6 +32,9 @@
 #define ADXL345_REG_DATA_AXIS(si)	\
 	(ADXL345_REG_DATAX0 + (si) * sizeof(__le16))
 
+#define ADXL345_BW_RATE			GENMASK(3, 0)
+#define ADXL345_BASE_RATE_NANO_HZ	97656250LL
+
 #define ADXL345_POWER_CTL_MEASURE	BIT(3)
 #define ADXL345_POWER_CTL_STANDBY	0x00
 

@@ -61,7 +66,8 @@ struct adxl345_data {
 	.channel2 = IIO_MOD_##axis,					\
 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
 		BIT(IIO_CHAN_INFO_CALIBBIAS),				\
-	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\
+	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |		\
+		BIT(IIO_CHAN_INFO_SAMP_FREQ),				\
 	.scan_index = si,						\
 }
 

@@ -77,6 +83,7 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
 {
 	struct adxl345_data *data = iio_priv(indio_dev);
 	__le16 accel;
+	long long samp_freq_nhz;
 	unsigned int regval;
 	int ret;
 

@@ -113,6 +120,16 @@ static int adxl345_read_raw(struct iio_dev *indio_dev,
 		*val = sign_extend32(regval, 7) * 4;
 
 		return IIO_VAL_INT;
+	case IIO_CHAN_INFO_SAMP_FREQ:
+		ret = regmap_read(data->regmap, ADXL345_REG_BW_RATE, &regval);
+		if (ret < 0)
+			return ret;
+
+		samp_freq_nhz = ADXL345_BASE_RATE_NANO_HZ <<
+				(regval & ADXL345_BW_RATE);
+		*val = div_s64_rem(samp_freq_nhz, 1000000000, val2);
+
+		return IIO_VAL_INT_PLUS_NANO;
 	}
 
 	return -EINVAL;

@@ -123,6 +140,7 @@ static int adxl345_write_raw(struct iio_dev *indio_dev,
 			    int val, int val2, long mask)
 {
 	struct adxl345_data *data = iio_priv(indio_dev);
+	int i;
 
 	switch (mask) {
 	case IIO_CHAN_INFO_CALIBBIAS:

@@ -133,14 +151,57 @@ static int adxl345_write_raw(struct iio_dev *indio_dev,
 		return regmap_write(data->regmap,
 				    ADXL345_REG_OFSX + chan->scan_index,
 				    val / 4);
+	case IIO_CHAN_INFO_SAMP_FREQ:
+		for (i = 0; i <= ADXL345_BW_RATE; i++) {
+			int nhz;
+			int hz;
+
+			hz = div_s64_rem(ADXL345_BASE_RATE_NANO_HZ << i,
+					 1000000000, &nhz);
+			if (hz == val && nhz == val2) {
+				return regmap_update_bits(data->regmap,
+							ADXL345_REG_BW_RATE,
+							ADXL345_BW_RATE, i);
+			}
+		}
+		return -EINVAL;
 	}
 
 	return -EINVAL;
 }
 
+static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev,
+				     struct iio_chan_spec const *chan,
+				     long mask)
+{
+	switch (mask) {
+	case IIO_CHAN_INFO_CALIBBIAS:
+		return IIO_VAL_INT;
+	case IIO_CHAN_INFO_SAMP_FREQ:
+		return IIO_VAL_INT_PLUS_NANO;
+	default:
+		return -EINVAL;
+	}
+}
+
+static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
+"0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600 3200"
+);
+
+static struct attribute *adxl345_attrs[] = {
+	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
+	NULL,
+};
+
+static const struct attribute_group adxl345_attrs_group = {
+	.attrs = adxl345_attrs,
+};
+
 static const struct iio_info adxl345_info = {
+	.attrs		= &adxl345_attrs_group,
 	.read_raw	= adxl345_read_raw,
 	.write_raw	= adxl345_write_raw,
+	.write_raw_get_fmt	= adxl345_write_raw_get_fmt,
 };
 
 int adxl345_core_probe(struct device *dev, struct regmap *regmap,
Signature · 1 line
2.7.4