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FAILED: patch "[PATCH] powerpc/64s/hash: Do not use PPC_INVALIDATE_ERAT on CPUs" failed to apply to 4.14-stable tree

PATCH [email protected] 1 participant 1 message Nov 11, 2018

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The patch below does not apply to the 4.14-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From bc276ecba132caccb1fda5863a652c15def2b8c6 Mon Sep 17 00:00:00 2001

From: Nicholas Piggin <[email protected]>
Date: Mon, 27 Aug 2018 13:03:01 +1000
Subject: [PATCH] powerpc/64s/hash: Do not use PPC_INVALIDATE_ERAT on CPUs
before POWER9

PPC_INVALIDATE_ERAT is slbia IH=7 which is a new variant introduced with POWER9, and the result is undefined on earlier CPUs.

Commits 7b9f71f974 ("powerpc/64s: POWER9 machine check handler") and d4748276ae ("powerpc/64s: Improve local TLB flush for boot and MCE on POWER9") caused POWER7/8 code to use this instruction. Remove it. An ERAT flush can be made by invalidatig the SLB, but before POWER9 that requires a flush and rebolt.

Fixes 7b9f71f974 ("powerpc/64s: POWER9 machine check handler")
Fixes d4748276ae ("powerpc/64s: Improve local TLB flush for boot and MCE on POWER9")
Cc [email protected] # v4.11+
Signed-off-by Nicholas Piggin <[email protected]>
Signed-off-by Michael Ellerman <[email protected]>
arch/powerpc/kernel/mce_power.c +7 -0
index 2016b58d564f..6b800eec31f2 100644
@@ -89,6 +89,13 @@ void flush_and_reload_slb(void)
 
 static void flush_erat(void)
 {
+#ifdef CONFIG_PPC_BOOK3S_64
+	if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) {
+		flush_and_reload_slb();
+		return;
+	}
+#endif
+	/* PPC_INVALIDATE_ERAT can only be used on ISA v3 and newer */
 	asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
 }
arch/powerpc/mm/hash_native_64.c +2 -2
index 729f02df8290..aaa28fd918fe 100644
@@ -115,6 +115,8 @@ static void tlbiel_all_isa300(unsigned int num_sets, unsigned int is)
 	tlbiel_hash_set_isa300(0, is, 0, 2, 1);
 
 	asm volatile("ptesync": : :"memory");
+
+	asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
 }
 
 void hash__tlbiel_all(unsigned int action)

@@ -140,8 +142,6 @@ void hash__tlbiel_all(unsigned int action)
 		tlbiel_all_isa206(POWER7_TLB_SETS, is);
 	else
 		WARN(1, "%s called on pre-POWER7 CPU\n", __func__);
-
-	asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
 }
 
 static inline unsigned long  ___tlbie(unsigned long vpn, int psize,