drm/amd/pp: Fix truncated clock value when set watermark
Subsystems (2)
PATCH 1/1 drm/amd/pp: Fix truncated clock value when set watermark
the clk value should be tranferred to MHz first and then transfer to uint16. otherwise, the clock value will be truncated.
--- drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c +16 -16
@@ -713,20 +713,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,for (i =0 ; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) { table->WatermarkRow[1 ][i].MinClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].MaxClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].MinUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].MaxUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].WmSetting = (uint8_t ) wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; }
@@ -734,20 +734,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,for (i =0 ; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) { table->WatermarkRow[0 ][i].MinClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].MaxClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].MinUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].MaxUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].WmSetting = (uint8_t ) wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; }
Signature · 6 lines
1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Alex Deucher
Reviewed-byQuoted 7 lines · Rex Zhu
the clk value should be tranferred to MHz first and then transfer to uint16. otherwise, the clock value will be truncated.
Reported-by Hersen Wu <[email protected]>Signed-off-by Rex Zhu <[email protected]>
Quoted 69 lines
--- drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-)drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c +16
-17@@ -713,20 +713,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,for (i =0 ; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) { table->WatermarkRow[1 ][i].MinClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].MaxClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].MinUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].MaxUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].WmSetting = (uint8_t ) wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; }@@ -734,20 +734,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,for (i =0 ; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) { table->WatermarkRow[0 ][i].MinClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].MaxClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].MinUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].MaxUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].WmSetting = (uint8_t ) wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; } --1.9.1
Quoted 4 lines
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Wentland, Harry
Reviewed-by Harry WentlandQuoted 6 lines · Rex Zhu
the clk value should be tranferred to MHz first and then transfer to uint16. otherwise, the clock value will be truncated.
Reported-by Hersen Wu <[email protected]>Signed-off-by Rex Zhu <[email protected]>
Harry
Quoted 57 lines
--- drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 32 ++++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-)drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c +13
-14@@ -713,20 +713,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,for (i =0 ; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) { table->WatermarkRow[1 ][i].MinClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].MaxClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].MinUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].MaxUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz / +1000 )); table->WatermarkRow[1 ][i].WmSetting = (uint8_t ) wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_set_id; }@@ -734,20 +734,20 @@ int smu_set_watermarks_for_clocks_ranges(void *wt_table,for (i =0 ; i < wm_with_clock_ranges->num_wm_mcif_sets; i++) { table->WatermarkRow[0 ][i].MinClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_socclk_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].MaxClock =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_socclk_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].MinUclk = cpu_to_le16((uint16_t) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_min_mem_clk_in_khz /
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int smu_set_watermarks_for_clocks_ranges(void *wt_table, · line 753
Quoted 10 lines
drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c +3
-2+ 1000)); table->WatermarkRow[0 ][i].MaxUclk =cpu_to_le16 ((uint16_t ) - (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz) / -1000 ); + (wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_max_mem_clk_in_khz / +1000 )); table->WatermarkRow[0 ][i].WmSetting = (uint8_t ) wm_with_clock_ranges->wm_mcif_clocks_ranges[i].wm_set_id; }
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