clk: qcom: Fix MSM8998 resets
Subsystems (3)
PATCH v2 1/1 clk: qcom: Fix MSM8998 resets
The offsets for the defined BCR reset registers does not match the hardware documentation. Update the values to match the hardware documentation.
Fixes b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)
Signed-off-by Jeffrey Hugo <[email protected]>
Reviewed-by Bjorn Andersson <[email protected]>
---
v2:
-Fixed GCC_PCIE_0_BCR per Bjorn and added his reviewed-by
drivers/clk/qcom/gcc-msm8998.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-)
drivers/clk/qcom/gcc-msm8998.c +19 -19
@@ -2742,25 +2742,25 @@ enum { };static const struct qcom_reset_map gcc_msm8998_resets[] = { - [GCC_BLSP1_QUP1_BCR ] = {0x102400 }, - [GCC_BLSP1_QUP2_BCR ] = {0x110592 }, - [GCC_BLSP1_QUP3_BCR ] = {0x118784 }, - [GCC_BLSP1_QUP4_BCR ] = {0x126976 }, - [GCC_BLSP1_QUP5_BCR ] = {0x135168 }, - [GCC_BLSP1_QUP6_BCR ] = {0x143360 }, - [GCC_BLSP2_QUP1_BCR ] = {0x155648 }, - [GCC_BLSP2_QUP2_BCR ] = {0x163840 }, - [GCC_BLSP2_QUP3_BCR ] = {0x172032 }, - [GCC_BLSP2_QUP4_BCR ] = {0x180224 }, - [GCC_BLSP2_QUP5_BCR ] = {0x188416 }, - [GCC_BLSP2_QUP6_BCR ] = {0x196608 }, - [GCC_PCIE_0_BCR ] = {0x438272 }, - [GCC_PDM_BCR ] = {0x208896 }, - [GCC_SDCC2_BCR ] = {0x81920 }, - [GCC_SDCC4_BCR ] = {0x90112 }, - [GCC_TSIF_BCR ] = {0x221184 }, - [GCC_UFS_BCR ] = {0x479232 }, - [GCC_USB_30_BCR ] = {0x61440 }, + [GCC_BLSP1_QUP1_BCR ] = {0x19000 }, + [GCC_BLSP1_QUP2_BCR ] = {0x1b000 }, + [GCC_BLSP1_QUP3_BCR ] = {0x1d000 }, + [GCC_BLSP1_QUP4_BCR ] = {0x1f000 }, + [GCC_BLSP1_QUP5_BCR ] = {0x21000 }, + [GCC_BLSP1_QUP6_BCR ] = {0x23000 }, + [GCC_BLSP2_QUP1_BCR ] = {0x26000 }, + [GCC_BLSP2_QUP2_BCR ] = {0x28000 }, + [GCC_BLSP2_QUP3_BCR ] = {0x2a000 }, + [GCC_BLSP2_QUP4_BCR ] = {0x2c000 }, + [GCC_BLSP2_QUP5_BCR ] = {0x2e000 }, + [GCC_BLSP2_QUP6_BCR ] = {0x30000 }, + [GCC_PCIE_0_BCR ] = {0x6b000 }, + [GCC_PDM_BCR ] = {0x33000 }, + [GCC_SDCC2_BCR ] = {0x14000 }, + [GCC_SDCC4_BCR ] = {0x16000 }, + [GCC_TSIF_BCR ] = {0x36000 }, + [GCC_UFS_BCR ] = {0x75000 }, + [GCC_USB_30_BCR ] = {0xf000 }, };static const struct regmap_config gcc_msm8998_regmap_config = {
Signature · 3 lines
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
Quoting Jeffrey Hugo (2018-12-03 08:13:43)
Quoted 7 lines
The offsets for the defined BCR reset registers does not match the hardware documentation. Update the values to match the hardware documentation.
Fixes b5f5f525c547 (clk: qcom: Add MSM8998 Global Clock Control (GCC) driver)Signed-off-by Jeffrey Hugo <[email protected]>Reviewed-by Bjorn Andersson <[email protected]>---
Applied to clk-next