clk: aspeed: Setup video engine clocking
Subsystems (3)
cover clk: aspeed: Setup video engine clocking
This series adds the parent clock definitions and muxing for the AST2xxx video engine.
I sent this series before as part of my first patch set for the video engine, but probably better to send it separately.
Eddie James (2):
clk: aspeed: Add video engine reset index definition
clk: aspeed: Setup video engine clocking
drivers/clk/clk-aspeed.c | 41 ++++++++++++++++++++++++++++++-- include/dt-bindings/clock/aspeed-clock.h | 1 + 2 files changed, 40 insertions(+), 2 deletions(-)
Signature · 1 line
1.8.3.1
PATCH 1/2 clk: aspeed: Add video engine reset index definition
Add an index into the array of resets kept in the Aspeed clock driver for the video engine. This isn't a HW bit definition.
--- include/dt-bindings/clock/aspeed-clock.h | 1 + 1 file changed, 1 insertion(+)
include/dt-bindings/clock/aspeed-clock.h +1 -0
@@ -50,5 +50,6 @@#define ASPEED_RESET_I2C 7#define ASPEED_RESET_AHB 8#define ASPEED_RESET_CRT1 9 +#define ASPEED_RESET_VIDEO 10#endif
Signature · 1 line
1.8.3.1
PATCH 2/2 clk: aspeed: Setup video engine clocking
In reply to Eddie JamesAdd the video engine reset bit. Add eclk mux and clock divider table.
--- drivers/clk/clk-aspeed.c | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-)
drivers/clk/clk-aspeed.c +39 -2
@@ -87,7 +87,7 @@ struct aspeed_clk_gate {/* TODO: ask Aspeed about the actual parent data */ static const struct aspeed_gate_data aspeed_gates[] = {/* clk rst name parent flags */ - [ASPEED_CLK_GATE_ECLK ] = {0 ,-1 ,"eclk-gate" ,"eclk" ,0 },/* Video Engine */ + [ASPEED_CLK_GATE_ECLK ] = {0 ,6 ,"eclk-gate" ,"eclk" ,0 },/* Video Engine */ [ASPEED_CLK_GATE_GCLK ] = {1 ,7 ,"gclk-gate" ,NULL ,0 },/* 2D engine */ [ASPEED_CLK_GATE_MCLK ] = {2 ,-1 ,"mclk-gate" ,"mpll" ,CLK_IS_CRITICAL },/* SDRAM */ [ASPEED_CLK_GATE_VCLK ] = {3 ,6 ,"vclk-gate" ,NULL ,0 },/* Video Capture */
@@ -113,6 +113,24 @@ struct aspeed_clk_gate { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const char *const eclk_parent_names[] = { +"mpll" , +"hpll" , +"dpll" , +}; + +static const struct clk_div_table ast2500_eclk_div_table[] = { + {0x0 ,2 }, + {0x1 ,2 }, + {0x2 ,3 }, + {0x3 ,4 }, + {0x4 ,5 }, + {0x5 ,6 }, + {0x6 ,7 }, + {0x7 ,8 }, + {0 } +}; +static const struct clk_div_table ast2500_mac_div_table[] = { {0x0 ,4 },/* Yep, really. Aspeed confirmed this is correct */ {0x1 ,4 },
@@ -192,18 +210,21 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)struct aspeed_clk_soc_data {const struct clk_div_table *div_table; +const struct clk_div_table *eclk_div_table;const struct clk_div_table *mac_div_table;struct clk_hw *(*calc_pll)(const char *name,u32 val); };static const struct aspeed_clk_soc_data ast2500_data = { .div_table = ast2500_div_table, + .eclk_div_table = ast2500_eclk_div_table, .mac_div_table = ast2500_mac_div_table, .calc_pll = aspeed_ast2500_calc_pll, };static const struct aspeed_clk_soc_data ast2400_data = { .div_table = ast2400_div_table, + .eclk_div_table = ast2400_div_table, .mac_div_table = ast2400_div_table, .calc_pll = aspeed_ast2400_calc_pll, };
@@ -317,6 +338,7 @@ struct aspeed_reset { [ASPEED_RESET_PECI] = 10, [ASPEED_RESET_I2C] = 2, [ASPEED_RESET_AHB] = 1, + [ASPEED_RESET_VIDEO] = 6,/* * SCUD4 resets start at an offset to separate them from
@@ -522,6 +544,22 @@ static int aspeed_clk_probe(struct platform_device *pdev)return PTR_ERR (hw); aspeed_clk_data->hws[ASPEED_CLK_24M ] = hw; + hw =clk_hw_register_mux (dev,"eclk-mux" , eclk_parent_names, +ARRAY_SIZE (eclk_parent_names),0 , + scu_base +ASPEED_CLK_SELECTION ,2 ,0x3 ,0 , + &aspeed_clk_lock); +if (IS_ERR (hw)) +return PTR_ERR (hw); + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX ] = hw; + + hw =clk_hw_register_divider_table (dev,"eclk" ,"eclk-mux" ,0 , + scu_base +ASPEED_CLK_SELECTION ,28 , +3 ,0 , soc_data->eclk_div_table, + &aspeed_clk_lock); +if (IS_ERR (hw)) +return PTR_ERR (hw); + aspeed_clk_data->hws[ASPEED_CLK_ECLK ] = hw; +/* * TODO: There are a number of clocks that not included in this driver * as more information is required:
@@ -531,7 +569,6 @@ static int aspeed_clk_probe(struct platform_device *pdev)* RGMII * RMII * UART[1..5] clock source mux -* Video Engine (ECLK) mux and clock divider */ for (i =0 ; i <ARRAY_SIZE (aspeed_gates); i++) {
Signature · 1 line
1.8.3.1
Joel Stanley
maintainerHi Eddie,
Quoted 25 lines · Eddie James
Add the video engine reset bit. Add eclk mux and clock divider table.
Signed-off-by Eddie James <[email protected]>Acked-by Stephen Boyd <[email protected]>--- drivers/clk/clk-aspeed.c | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-)drivers/clk/clk-aspeed.c +1
-1@@ -87,7 +87,7 @@ struct aspeed_clk_gate {/* TODO: ask Aspeed about the actual parent data */ static const struct aspeed_gate_data aspeed_gates[] = {/* clk rst name parent flags */ - [ASPEED_CLK_GATE_ECLK ] = {0 ,-1 ,"eclk-gate" ,"eclk" ,0 },/* Video Engine */ + [ASPEED_CLK_GATE_ECLK ] = {0 ,6 ,"eclk-gate" ,"eclk" ,0 },/* Video Engine */ [ASPEED_CLK_GATE_GCLK ] = {1 ,7 ,"gclk-gate" ,NULL ,0 },/* 2D engine */ [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
drivers/clk/clk-aspeed.c struct aspeed_clk_gate { · line 117
Quoted 5 lines
drivers/clk/clk-aspeed.c +2
-0@@ -113,6 +113,24 @@ struct aspeed_clk_gate { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const char *const eclk_parent_names[] = { +"mpll" ,
Is the mpll really an input to the eclk?
drivers/clk/clk-aspeed.c struct aspeed_clk_gate { · line 119
Quoted 2 lines
drivers/clk/clk-aspeed.c +2
-0+"hpll" , + "dpll",
We don't have a dpll in the driver that I can see.
drivers/clk/clk-aspeed.c struct aspeed_clk_gate { · line 122
Quoted 3 lines
drivers/clk/clk-aspeed.c +3
-0+}; + +static const struct clk_div_table ast2500_eclk_div_table[] = {
Is the clocking setup different on the ast2400?
Quoted 12 lines
drivers/clk/clk-aspeed.c +10
-0+ { 0x0, 2 }, + { 0x1, 2 }, + { 0x2, 3 }, + { 0x3, 4 }, + { 0x4, 5 }, + { 0x5, 6 }, + { 0x6, 7 }, + { 0x7, 8 }, + { 0 } +};
drivers/clk/clk-aspeed.c struct aspeed_reset { · line 341
Quoted 4 lines
drivers/clk/clk-aspeed.c +1
-0@@ -317,6 +338,7 @@ struct aspeed_reset { [ASPEED_RESET_PECI] = 10, [ASPEED_RESET_I2C] = 2, [ASPEED_RESET_AHB] = 1, + [ASPEED_RESET_VIDEO] = 6,
You've added the reset line to the ASPEED_CLK_GATE_ECLK clock so you do not need to separately expose the reset controller. Instead enabling the clock will deassert the rest line for you.
This means you should drop the change from the header too, and it affects the bindings document for the video engine.
Quoted 37 lines
drivers/clk/clk-aspeed.c +16
-2/* * SCUD4 resets start at an offset to separate them from @@ -522,6 +544,22 @@ static int aspeed_clk_probe(struct platform_device *pdev)return PTR_ERR (hw); aspeed_clk_data->hws[ASPEED_CLK_24M ] = hw; + hw =clk_hw_register_mux (dev,"eclk-mux" , eclk_parent_names, +ARRAY_SIZE (eclk_parent_names),0 , + scu_base +ASPEED_CLK_SELECTION ,2 ,0x3 ,0 , + &aspeed_clk_lock); +if (IS_ERR (hw)) +return PTR_ERR (hw); + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX ] = hw; + + hw =clk_hw_register_divider_table (dev,"eclk" ,"eclk-mux" ,0 , + scu_base +ASPEED_CLK_SELECTION ,28 , +3 ,0 , soc_data->eclk_div_table, + &aspeed_clk_lock); +if (IS_ERR (hw)) +return PTR_ERR (hw); + aspeed_clk_data->hws[ASPEED_CLK_ECLK ] = hw; +/* * TODO: There are a number of clocks that not included in this driver * as more information is required: @@ -531,7 +569,6 @@ static int aspeed_clk_probe(struct platform_device *pdev)* RGMII * RMII * UART[1..5] clock source mux -* Video Engine (ECLK) mux and clock divider */ for (i =0 ; i <ARRAY_SIZE (aspeed_gates); i++) { --1.8.3.1
Quoted 29 lines · Joel Stanley
Hi Eddie,
Quoted 26 lines · Eddie James
Add the video engine reset bit. Add eclk mux and clock divider table.
Signed-off-by Eddie James <[email protected]>Acked-by Stephen Boyd <[email protected]>--- drivers/clk/clk-aspeed.c | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-)drivers/clk/clk-aspeed.c +1
-1@@ -87,7 +87,7 @@ struct aspeed_clk_gate {/* TODO: ask Aspeed about the actual parent data */ static const struct aspeed_gate_data aspeed_gates[] = {/* clk rst name parent flags */ - [ASPEED_CLK_GATE_ECLK ] = {0 ,-1 ,"eclk-gate" ,"eclk" ,0 },/* Video Engine */ + [ASPEED_CLK_GATE_ECLK ] = {0 ,6 ,"eclk-gate" ,"eclk" ,0 },/* Video Engine */ [ASPEED_CLK_GATE_GCLK ] = {1 ,7 ,"gclk-gate" ,NULL ,0 },/* 2D engine */ [ASPEED_CLK_GATE_MCLK ] = {2 ,-1 ,"mclk-gate" ,"mpll" ,CLK_IS_CRITICAL },/* SDRAM */ [
ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */drivers/clk/clk-aspeed.c +0
-0@@ -113,6 +113,24 @@ struct aspeed_clk_gate { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ };
Quoted 3 lines
drivers/clk/clk-aspeed.c struct aspeed_clk_gate { · line 117
Quoted 2 lines
drivers/clk/clk-aspeed.c +2
-0+static const char *const eclk_parent_names[] = { +"mpll" ,Is the mpll really an input to the eclk?
Yep, it's the default.
Quoted 4 lines
drivers/clk/clk-aspeed.c struct aspeed_clk_gate { · line 119
Quoted 3 lines
drivers/clk/clk-aspeed.c +2
-0+"hpll" , + "dpll",We don't have a dpll in the driver that I can see.
True... I supposed I would just add the parent here now in case the dpll clock is ever added.
Quoted 5 lines
drivers/clk/clk-aspeed.c struct aspeed_clk_gate { · line 122
Quoted 4 lines
drivers/clk/clk-aspeed.c +3
-0+}; + +static const struct clk_div_table ast2500_eclk_div_table[] = {Is the clocking setup different on the ast2400?
Yes, the dividers are the default ast2400 ones.
Quoted 20 lines
Quoted 12 lines
drivers/clk/clk-aspeed.c +10
-0+ { 0x0, 2 }, + { 0x1, 2 }, + { 0x2, 3 }, + { 0x3, 4 }, + { 0x4, 5 }, + { 0x5, 6 }, + { 0x6, 7 }, + { 0x7, 8 }, + { 0 } +};drivers/clk/clk-aspeed.c struct aspeed_reset { · line 341
Quoted 4 lines
drivers/clk/clk-aspeed.c +1
-0@@ -317,6 +338,7 @@ struct aspeed_reset { [ASPEED_RESET_PECI] = 10, [ASPEED_RESET_I2C] = 2, [ASPEED_RESET_AHB] = 1, + [ASPEED_RESET_VIDEO] = 6,You've added the reset line to the
ASPEED_CLK_GATE_ECLKclock so you do not need to separately expose the reset controller. Instead enabling the clock will deassert the rest line for you.
Quoted 2 lines
This means you should drop the change from the header too, and it affects the bindings document for the video engine.
I want that reset available separately for use in the video engine actually. I could do without it, but it's somewhat useful.
Thanks,
Eddie
Quoted 37 lines
Quoted 37 lines
drivers/clk/clk-aspeed.c +16
-2/* * SCUD4 resets start at an offset to separate them from @@ -522,6 +544,22 @@ static int aspeed_clk_probe(struct platform_device *pdev)return PTR_ERR (hw); aspeed_clk_data->hws[ASPEED_CLK_24M ] = hw; + hw =clk_hw_register_mux (dev,"eclk-mux" , eclk_parent_names, +ARRAY_SIZE (eclk_parent_names),0 , + scu_base +ASPEED_CLK_SELECTION ,2 ,0x3 ,0 , + &aspeed_clk_lock); +if (IS_ERR (hw)) +return PTR_ERR (hw); + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX ] = hw; + + hw =clk_hw_register_divider_table (dev,"eclk" ,"eclk-mux" ,0 , + scu_base +ASPEED_CLK_SELECTION ,28 , +3 ,0 , soc_data->eclk_div_table, + &aspeed_clk_lock); +if (IS_ERR (hw)) +return PTR_ERR (hw); + aspeed_clk_data->hws[ASPEED_CLK_ECLK ] = hw; +/* * TODO: There are a number of clocks that not included in this driver * as more information is required: @@ -531,7 +569,6 @@ static int aspeed_clk_probe(struct platform_device *pdev)* RGMII * RMII * UART[1..5] clock source mux -* Video Engine (ECLK) mux and clock divider */ for (i =0 ; i <ARRAY_SIZE (aspeed_gates); i++) { --1.8.3.1
Stephen Boyd
maintainerQuoting Eddie James (2018-12-14 07:47:53)
Quoted 24 lines · Joel Stanley
Quoted 21 lines
Quoted 13 lines
drivers/clk/clk-aspeed.c +10
-0+ { 0x0, 2 }, + { 0x1, 2 }, + { 0x2, 3 }, + { 0x3, 4 }, + { 0x4, 5 }, + { 0x5, 6 }, + { 0x6, 7 }, + { 0x7, 8 }, + { 0 } +};drivers/clk/clk-aspeed.c struct aspeed_reset { · line 341
Quoted 4 lines
drivers/clk/clk-aspeed.c +1
-0@@ -317,6 +338,7 @@ struct aspeed_reset { [ASPEED_RESET_PECI] = 10, [ASPEED_RESET_I2C] = 2, [ASPEED_RESET_AHB] = 1, + [ASPEED_RESET_VIDEO] = 6,You've added the reset line to the
ASPEED_CLK_GATE_ECLKclock so you do not need to separately expose the reset controller. Instead enabling the clock will deassert the rest line for you.
Quoted 6 lines
Quoted 2 lines
This means you should drop the change from the header too, and it affects the bindings document for the video engine.
I want that reset available separately for use in the video engine actually. I could do without it, but it's somewhat useful.
Joel, are you happy with these patches? I'm tempted to drop these changes from my queue because there hasn't been any news in over a month.