clk: qcom: gcc: Use active only source for CPUSS clocks
Subsystems (3)
PATCH 1/1 clk: qcom: gcc: Use active only source for CPUSS clocks
The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL clock and needs to vote on the active only source of XO, so as to keep the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has the same requirement.
Signed-off-by Taniya Das <[email protected]>
--- drivers/clk/qcom/gcc-sdm845.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-)
drivers/clk/qcom/gcc-sdm845.c +10 -4
@@ -115,8 +115,8 @@ enum { "core_bi_pll_test_se", }; -static const char *const gcc_parent_names_7[] = { -"bi_tcxo" , +static const char *const gcc_parent_names_7_ao[] = { +"bi_tcxo_ao" ,"gpll0" ,"gpll0_out_even" ,"core_bi_pll_test_se" ,
@@ -128,6 +128,12 @@ enum { "core_bi_pll_test_se", }; +static const char *const gcc_parent_names_8_ao[] = { +"bi_tcxo_ao" , +"gpll0" , +"core_bi_pll_test_se" , +}; +static const struct parent_map gcc_parent_map_10[] = { {P_BI_TCXO ,0 }, {P_GPLL0_OUT_MAIN ,1 },
@@ -210,7 +216,7 @@ enum { .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data ){ .name ="gcc_cpuss_ahb_clk_src" , - .parent_names = gcc_parent_names_7, + .parent_names = gcc_parent_names_7_ao, .num_parents =4 , .ops = &clk_rcg2_ops, },
@@ -229,7 +235,7 @@ enum { .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, .clkr.hw.init = &(struct clk_init_data ){ .name ="gcc_cpuss_rbcpr_clk_src" , - .parent_names = gcc_parent_names_8, + .parent_names = gcc_parent_names_8_ao, .num_parents =3 , .ops = &clk_rcg2_ops, },
--
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Quoting Taniya Das (2018-12-18 10:19:41)
Quoted 7 lines
The clocks of the CPUSS such as "
gcc_cpuss_ahb_clk_src" is a CRITICAL clock and needs to vote on the active only source of XO, so as to keep the vote as long as CPUSS is active. Similarrbcpr_clk_srcis also has the same requirement.Signed-off-by Taniya Das <[email protected]>---
Applied to clk-fixes + added a Fixes tag.