patch "staging: mt7621-pci-phy: dt-bindings: add bindings for Mediatek" added to staging-next
Subsystems (2)
This is a note to let you know that I've just added the patch titled
staging: mt7621-pci-phy: dt-bindings: add bindings for Mediatek
to my staging git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
in the staging-next branch.
The patch will show up in the next release of the linux-next tree (usually sometime within the next 24 hours during the week.)
The patch will also be merged in the next major kernel release during the merge window.
If you have any questions about this process, please let me know.
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From
9e2ddbdd9218bf0e465d19daecdd053052ffd79cMon Sep 17 00:00:00 2001
From: Sergio Paracuellos <[email protected]>
Date: Fri, 4 Jan 2019 08:08:24 +0100
Subject: staging: mt7621-pci-phy: dt-bindings: add bindings for Mediatek
MT7621 Pcie PHY
Add bindings documentation for PCie PHY of Mediatek MT7621. This file will be moved into its appropiate documentation bindings'place when this driver is mainlined.
--- .../mediatek,mt7621-pci-phy.txt | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt
drivers/staging/mt7621-pci-phy/mediatek,mt7621-pci-phy.txt new file +54 -0
@@ -0,0 +1,54 @@ +Mediatek Mt7621 PCIe PHY + +Required properties: +- compatible: must be "mediatek,mt7621-pci-phy" +- reg: base address and length of the PCIe PHY block +- #address-cells: must be 1 +- #size-cells: must be 0 + +Each PCIe PHY should be represented by a child node + +Required properties For the child node: +- reg: the PHY ID +0 - PCIe RC 0 +1 - PCIe RC 1 +- #phy-cells: must be 0 + +Example: + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1a149000 0x0700>; + #address-cells = <1>; + #size-cells = <0>; + + pcie0_port: pcie-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + pcie1_port: pcie-phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1a14a000 0x0700>; + #address-cells = <1>; + #size-cells = <0>; + + pcie2_port: pcie-phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + }; + + /* users of the PCIe phy */ + + pcie: pcie@1e140000 { + ... + ... + phys = <&pcie0_port>, <&pcie1_port>, <&pcie2_port>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + };
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2.20.1