sc7180: Add A618 GPU bindings

From: Taniya Das <[email protected]>

In the cases where the GPU SW requires to use the GX GDSCR add support for the same.

Signed-off-by Taniya Das <[email protected]>

From: Taniya Das <[email protected]>

Most of the time the CPU should not be touching the GX domain on the GPU
except for a very special use case when the CPU needs to force the GX

headswitch off. Add a dummy enable function for the GX gdsc to simulate success so that the pm_runtime reference counting is correct.

Signed-off-by Taniya Das <[email protected]>

---
 drivers/clk/qcom/gpucc-sc7180.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

drivers/clk/qcom/gpucc-sc7180.c +20 -0

index ec61194..3b29f19 100644
@@ -172,8 +172,45 @@ enum {
        .flags = VOTABLE,
 };
 
+/*
+ * On SC7180 the GPU GX domain is *almost* entirely controlled by the GMU
+ * running in the CX domain so the CPU doesn't need to know anything about the
+ * GX domain EXCEPT....
+ *
+ * Hardware constraints dictate that the GX be powered down before the CX. If
+ * the GMU crashes it could leave the GX on. In order to successfully bring back
+ * the device the CPU needs to disable the GX headswitch. There being no sane
+ * way to reach in and touch that register from deep inside the GPU driver we
+ * need to set up the infrastructure to be able to ensure that the GPU can
+ * ensure that the GX is off during this super special case. We do this by
+ * defining a GX gdsc with a dummy enable function and a "default" disable
+ * function.
+ *
+ * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
+ * driver. During power up, nothing will happen from the CPU (and the GMU will
+ * power up normally but during power down this will ensure that the GX domain
+ * is *really* off - this gives us a semi standard way of doing what we need.
+ */
+static int gx_gdsc_enable(struct generic_pm_domain *domain)

This patch adds the required dt nodes and properties to enabled A618 GPU.

Signed-off-by Sharat Masetty <[email protected]>

---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)

arch/arm64/boot/dts/qcom/sc7180.dtsi +43 -0

index f3fcc5c..63fff15 100644
@@ -1043,6 +1043,108 @@
                        };
                };
 
+               gpu: gpu@5000000 {
+                       compatible = "qcom,adreno-618.0", "qcom,adreno";
+                       #stream-id-cells = <16>;
+                       reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
+                               <0 0x05061000 0 0x800>;
+                       reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
+                       interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+                       iommus = <&adreno_smmu 0>;
+                       operating-points-v2 = <&gpu_opp_table>;
+                       qcom,gmu = <&gmu>;
+
+                       gpu_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-800000000 {
+                                       opp-hz = /bits/ 64 <800000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+                               };
+
+                               opp-650000000 {
+                                       opp-hz = /bits/ 64 <650000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+                               };
+
+                               opp-565000000 {
+                                       opp-hz = /bits/ 64 <565000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+                               };
+
+                               opp-430000000 {
+                                       opp-hz = /bits/ 64 <430000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+                               };
+
+                               opp-355000000 {
+                                       opp-hz = /bits/ 64 <355000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+                               };
+
+                               opp-267000000 {
+                                       opp-hz = /bits/ 64 <267000000>;
+                                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+                               };

arch/arm64/boot/dts/qcom/sc7180.dtsi +8 -0

+                       reg = <0 0x05040000 0 0x10000>;
+                       #iommu-cells = <1>;
+                       #global-interrupts = <2>;
+                       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+                                       <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+                                       <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,

+ power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;

Hi,

Quoted 1 line · Sharat Masetty

Quoted 1 line

+ power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;

I should note that this is going to be a PITA to land because the patch adding "GX_GDSC" should technically land in the "clk" tree. Without extra work that's going to mean waiting for a full Linux release before Bjorn and Andy can land. It might be worth sticking the hardcoded "1" in for now instead of "GX_GDSC". That's what we often do in cases like this.