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clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk

PATCH Applied Taniya Das 3 participants 10 messages Feb 11, 2020 – Mar 16, 2020 1 message not in the archive

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Taniya Das

author
#0 lore raw

PATCH 1/2 clk: qcom: videocc: Update the clock flag for video_cc_vcodec0_core_clk

The clock disable signal for video_cc_vcodec0_core_clk is tied to vcodec0_gdsc which is supported in the HW control mode. Thus turning off the clock would be taken care automatically when the GDSC turns OFF by hardware and clock driver does not require to poll on the CLK_OFF bit.

Signed-off-by Taniya Das <[email protected]>
---
 drivers/clk/qcom/videocc-sc7180.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/qcom/videocc-sc7180.c +1 -1
index c363c3c..276e5ec 100644
@@ -97,7 +97,7 @@ static struct clk_branch video_cc_vcodec0_axi_clk = {
 
 static struct clk_branch video_cc_vcodec0_core_clk = {
 	.halt_reg = 0x890,
-	.halt_check = BRANCH_HALT,
+	.halt_check = BRANCH_HALT_VOTED,
 	.clkr = {
 		.enable_reg = 0x890,
 		.enable_mask = BIT(0),

--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.

author
#1 lore raw

PATCH 2/2 clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk

The disp_cc_mdss_rscc_ahb_clk is default enabled from hardware and thus does not require to be marked CRITICAL. This which would allow the RCG to be turned OFF when the display turns OFF and not blocking XO.

Signed-off-by Taniya Das <[email protected]>
---
 drivers/clk/qcom/dispcc-sc7180.c | 19 -------------------
 1 file changed, 19 deletions(-)
drivers/clk/qcom/dispcc-sc7180.c +0 -19
index dd7af41..0a5d395 100644
@@ -592,24 +592,6 @@ static struct clk_branch disp_cc_mdss_rot_clk = {
 	},
 };
 
-static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
-	.halt_reg = 0x400c,
-	.halt_check = BRANCH_HALT,
-	.clkr = {
-		.enable_reg = 0x400c,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "disp_cc_mdss_rscc_ahb_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
 	.halt_reg = 0x4008,
 	.halt_check = BRANCH_HALT,

@@ -687,7 +669,6 @@ static struct clk_regmap *disp_cc_sc7180_clocks[] = {
 	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
 	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
 	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
-	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
 	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
 	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
 	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,

--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.

maintainer Applied
#2 lore raw

Re: [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk

Quoting Taniya Das (2020-02-11 04:13:56)

Quoted 6 lines

The disp_cc_mdss_rscc_ahb_clk is default enabled from hardware and thus does not require to be marked CRITICAL. This which would allow the RCG to be turned OFF when the display turns OFF and not blocking XO.

Signed-off-by Taniya Das <[email protected]>

---

Applied to clk-fixes

#3 lore raw

Re: [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk

In reply to Taniya Das
Quoted 39 lines · Taniya Das

The disp_cc_mdss_rscc_ahb_clk is default enabled from hardware and thus does not require to be marked CRITICAL. This which would allow the RCG to be turned OFF when the display turns OFF and not blocking XO.

Signed-off-by Taniya Das <[email protected]>
---
 drivers/clk/qcom/dispcc-sc7180.c | 19 -------------------
 1 file changed, 19 deletions(-)
drivers/clk/qcom/dispcc-sc7180.c +0 -18
index dd7af41..0a5d395 100644
@@ -592,24 +592,6 @@ static struct clk_branch disp_cc_mdss_rot_clk = {
 	},
 };
 
-static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
-	.halt_reg = 0x400c,
-	.halt_check = BRANCH_HALT,
-	.clkr = {
-		.enable_reg = 0x400c,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "disp_cc_mdss_rscc_ahb_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
 	.halt_reg = 0x4008,
 	.halt_check = BRANCH_HALT,

drivers/clk/qcom/dispcc-sc7180.c static struct clk_regmap *disp_cc_sc7180_clocks[] = { · line 674

Quoted 7 lines
drivers/clk/qcom/dispcc-sc7180.c +0 -1
@@ -687,7 +669,6 @@ static struct clk_regmap *disp_cc_sc7180_clocks[] = {
 	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
 	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
 	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
-	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
 	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
 	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
 	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,

We found that this change leads to a panic at boot time on SC7180 devices without display configuration (e.g. the SC7180 IDP with the current DT):

[    2.412820] SError Interrupt on CPU6, code 0xbe000411 -- SError
[    2.412822] CPU: 6 PID: 1 Comm: swapper/0 Tainted: G S                5.4.22 #103
[    2.412822] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT)
[    2.412823] pstate: 20c00089 (nzCv daIf +PAN +UAO)
[    2.412823] pc : regmap_mmio_read32le+0x28/0x40
[    2.412823] lr : regmap_mmio_read+0x44/0x6c
[    2.412824] sp : ffffffc01005ba90
[    2.412824] x29: ffffffc01005ba90 x28: 0000000000000000
[    2.412825] x27: 0000000000000000 x26: 0000000000000000
[    2.412826] x25: 0000000000000000 x24: ffffffd1f4aed018
[    2.412827] x23: ffffffd1f4c12148 x22: ffffff8177a6c800
[    2.412827] x21: 0000000000002048 x20: ffffff8177489e00
[    2.412828] x19: 0000000000002048 x18: 000000004a746f4b
[    2.412829] x17: 00000000d0e09034 x16: 000000005079b450
[    2.412830] x15: 000000003e3bf7ed x14: 0000000000007fff
[    2.412830] x13: ffffff8177309b40 x12: 0000000000000000
[    2.412831] x11: 0000000000000000 x10: 0000000000000000
[    2.412831] x9 : 0000000000000001 x8 : ffffffc011c02048
[    2.412832] x7 : aaaaaaaaaaaaaaaa x6 : 0000000000000000
[    2.412833] x5 : 0000000000000000 x4 : 0000000000000000
[    2.412834] x3 : 0000000000000000 x2 : ffffffc01005bb84
[    2.412834] x1 : 0000000000002048 x0 : 0000000080000000
[    2.412835] Kernel panic - not syncing: Asynchronous SError Interrupt
[    2.412836] CPU: 6 PID: 1 Comm: swapper/0 Tainted: G S                5.4.22 #103
[    2.412836] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT)
[    2.412836] Call trace:
[    2.412837]  dump_backtrace+0x0/0x150
[    2.412837]  show_stack+0x20/0x2c
[    2.412837]  dump_stack+0xa0/0xd8
[    2.412838]  panic+0x158/0x360
[    2.412838]  panic+0x0/0x360
[    2.412838]  arm64_serror_panic+0x78/0x84
[    2.412839]  do_serror+0x110/0x118
[    2.412839]  el1_error+0x84/0xf8
[    2.412839]  regmap_mmio_read32le+0x28/0x40
[    2.412840]  regmap_mmio_read+0x44/0x6c
[    2.412840]  _regmap_bus_reg_read+0x34/0x44
[    2.412841]  _regmap_read+0x88/0x164
[    2.412841]  regmap_read+0x54/0x78
[    2.412841]  clk_is_enabled_regmap+0x3c/0x8c
[    2.412842]  clk_core_is_enabled+0x68/0xac
[    2.412842]  clk_disable_unused_subtree+0x90/0x22c
[    2.412843]  clk_disable_unused_subtree+0x34/0x22c
[    2.412843]  clk_disable_unused+0x74/0x108
[    2.412843]  do_one_initcall+0x13c/0x2c8
[    2.412844]  do_initcall_level+0x144/0x16c
[    2.412844]  do_basic_setup+0x30/0x48
[    2.412844]  kernel_init_freeable+0xc4/0x140
[    2.412845]  kernel_init+0x14/0x100
[    2.412845]  ret_from_fork+0x10/0x18
[    2.412858] SMP: stopping secondary CPUs
[    2.412859] Kernel Offset: 0x11e3a00000 from 0xffffffc010000000
[    2.412859] PHYS_OFFSET: 0xffffffe780000000
[    2.412860] CPU features: 0x0006,2a80aa18
[    2.412860] Memory Limit: none
author
#4 lore raw

Re: [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk

Quoted 98 lines · Matthias Kaehlcke
Quoted 39 lines · Taniya Das

The disp_cc_mdss_rscc_ahb_clk is default enabled from hardware and thus does not require to be marked CRITICAL. This which would allow the RCG to be turned OFF when the display turns OFF and not blocking XO.

Signed-off-by Taniya Das <[email protected]>
---
  drivers/clk/qcom/dispcc-sc7180.c | 19 -------------------
  1 file changed, 19 deletions(-)
drivers/clk/qcom/dispcc-sc7180.c +0 -18
index dd7af41..0a5d395 100644
@@ -592,24 +592,6 @@ static struct clk_branch disp_cc_mdss_rot_clk = {
  	},
  };
 
-static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
-	.halt_reg = 0x400c,
-	.halt_check = BRANCH_HALT,
-	.clkr = {
-		.enable_reg = 0x400c,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "disp_cc_mdss_rscc_ahb_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
  static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
  	.halt_reg = 0x4008,
  	.halt_check = BRANCH_HALT,

drivers/clk/qcom/dispcc-sc7180.c static struct clk_regmap *disp_cc_sc7180_clocks[] = { · line 674

Quoted 7 lines
drivers/clk/qcom/dispcc-sc7180.c +0 -1
@@ -687,7 +669,6 @@ static struct clk_regmap *disp_cc_sc7180_clocks[] = {
  	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
  	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
  	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
-	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
  	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
  	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
  	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,

We found that this change leads to a panic at boot time on SC7180 devices without display configuration (e.g. the SC7180 IDP with the current DT):

[    2.412820] SError Interrupt on CPU6, code 0xbe000411 -- SError
[    2.412822] CPU: 6 PID: 1 Comm: swapper/0 Tainted: G S                5.4.22 #103
[    2.412822] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT)
[    2.412823] pstate: 20c00089 (nzCv daIf +PAN +UAO)
[    2.412823] pc : regmap_mmio_read32le+0x28/0x40
[    2.412823] lr : regmap_mmio_read+0x44/0x6c
[    2.412824] sp : ffffffc01005ba90
[    2.412824] x29: ffffffc01005ba90 x28: 0000000000000000
[    2.412825] x27: 0000000000000000 x26: 0000000000000000
[    2.412826] x25: 0000000000000000 x24: ffffffd1f4aed018
[    2.412827] x23: ffffffd1f4c12148 x22: ffffff8177a6c800
[    2.412827] x21: 0000000000002048 x20: ffffff8177489e00
[    2.412828] x19: 0000000000002048 x18: 000000004a746f4b
[    2.412829] x17: 00000000d0e09034 x16: 000000005079b450
[    2.412830] x15: 000000003e3bf7ed x14: 0000000000007fff
[    2.412830] x13: ffffff8177309b40 x12: 0000000000000000
[    2.412831] x11: 0000000000000000 x10: 0000000000000000
[    2.412831] x9 : 0000000000000001 x8 : ffffffc011c02048
[    2.412832] x7 : aaaaaaaaaaaaaaaa x6 : 0000000000000000
[    2.412833] x5 : 0000000000000000 x4 : 0000000000000000
[    2.412834] x3 : 0000000000000000 x2 : ffffffc01005bb84
[    2.412834] x1 : 0000000000002048 x0 : 0000000080000000
[    2.412835] Kernel panic - not syncing: Asynchronous SError Interrupt
[    2.412836] CPU: 6 PID: 1 Comm: swapper/0 Tainted: G S                5.4.22 #103
[    2.412836] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT)
[    2.412836] Call trace:
[    2.412837]  dump_backtrace+0x0/0x150
[    2.412837]  show_stack+0x20/0x2c
[    2.412837]  dump_stack+0xa0/0xd8
[    2.412838]  panic+0x158/0x360
[    2.412838]  panic+0x0/0x360
[    2.412838]  arm64_serror_panic+0x78/0x84
[    2.412839]  do_serror+0x110/0x118
[    2.412839]  el1_error+0x84/0xf8
[    2.412839]  regmap_mmio_read32le+0x28/0x40
[    2.412840]  regmap_mmio_read+0x44/0x6c
[    2.412840]  _regmap_bus_reg_read+0x34/0x44
[    2.412841]  _regmap_read+0x88/0x164
[    2.412841]  regmap_read+0x54/0x78
[    2.412841]  clk_is_enabled_regmap+0x3c/0x8c
[    2.412842]  clk_core_is_enabled+0x68/0xac
[    2.412842]  clk_disable_unused_subtree+0x90/0x22c
[    2.412843]  clk_disable_unused_subtree+0x34/0x22c
[    2.412843]  clk_disable_unused+0x74/0x108
[    2.412843]  do_one_initcall+0x13c/0x2c8
[    2.412844]  do_initcall_level+0x144/0x16c
[    2.412844]  do_basic_setup+0x30/0x48
Quoted 9 lines
[    2.412844]  kernel_init_freeable+0xc4/0x140
[    2.412845]  kernel_init+0x14/0x100
[    2.412845]  ret_from_fork+0x10/0x18
[    2.412858] SMP: stopping secondary CPUs
[    2.412859] Kernel Offset: 0x11e3a00000 from 0xffffffc010000000
[    2.412859] PHYS_OFFSET: 0xffffffe780000000
[    2.412860] CPU features: 0x0006,2a80aa18
[    2.412860] Memory Limit: none

Hi Matthias,

The display device node is not present and we encounter this crash, would it be possible to add ALWAYS_ON for the MDSS GDSC and give it a try.

Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--
#5 lore raw

Re: [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk

Hi Taniya,

Quoted 110 lines · Taniya Das
Quoted 98 lines · Matthias Kaehlcke
Quoted 39 lines · Taniya Das

The disp_cc_mdss_rscc_ahb_clk is default enabled from hardware and thus does not require to be marked CRITICAL. This which would allow the RCG to be turned OFF when the display turns OFF and not blocking XO.

Signed-off-by Taniya Das <[email protected]>
---
  drivers/clk/qcom/dispcc-sc7180.c | 19 -------------------
  1 file changed, 19 deletions(-)
drivers/clk/qcom/dispcc-sc7180.c +0 -18
index dd7af41..0a5d395 100644
@@ -592,24 +592,6 @@ static struct clk_branch disp_cc_mdss_rot_clk = {
  	},
  };
 
-static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
-	.halt_reg = 0x400c,
-	.halt_check = BRANCH_HALT,
-	.clkr = {
-		.enable_reg = 0x400c,
-		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
-			.name = "disp_cc_mdss_rscc_ahb_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &disp_cc_mdss_ahb_clk_src.clkr.hw,
-			},
-			.num_parents = 1,
-			.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-			.ops = &clk_branch2_ops,
-		},
-	},
-};
-
  static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
  	.halt_reg = 0x4008,
  	.halt_check = BRANCH_HALT,

drivers/clk/qcom/dispcc-sc7180.c static struct clk_regmap *disp_cc_sc7180_clocks[] = { · line 674

Quoted 7 lines
drivers/clk/qcom/dispcc-sc7180.c +0 -1
@@ -687,7 +669,6 @@ static struct clk_regmap *disp_cc_sc7180_clocks[] = {
  	[DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
  	[DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
  	[DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
-	[DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
  	[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
  	[DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
  	[DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,

We found that this change leads to a panic at boot time on SC7180 devices without display configuration (e.g. the SC7180 IDP with the current DT):

[    2.412820] SError Interrupt on CPU6, code 0xbe000411 -- SError
[    2.412822] CPU: 6 PID: 1 Comm: swapper/0 Tainted: G S                5.4.22 #103
[    2.412822] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT)
[    2.412823] pstate: 20c00089 (nzCv daIf +PAN +UAO)
[    2.412823] pc : regmap_mmio_read32le+0x28/0x40
[    2.412823] lr : regmap_mmio_read+0x44/0x6c
[    2.412824] sp : ffffffc01005ba90
[    2.412824] x29: ffffffc01005ba90 x28: 0000000000000000
[    2.412825] x27: 0000000000000000 x26: 0000000000000000
[    2.412826] x25: 0000000000000000 x24: ffffffd1f4aed018
[    2.412827] x23: ffffffd1f4c12148 x22: ffffff8177a6c800
[    2.412827] x21: 0000000000002048 x20: ffffff8177489e00
[    2.412828] x19: 0000000000002048 x18: 000000004a746f4b
[    2.412829] x17: 00000000d0e09034 x16: 000000005079b450
[    2.412830] x15: 000000003e3bf7ed x14: 0000000000007fff
[    2.412830] x13: ffffff8177309b40 x12: 0000000000000000
[    2.412831] x11: 0000000000000000 x10: 0000000000000000
[    2.412831] x9 : 0000000000000001 x8 : ffffffc011c02048
[    2.412832] x7 : aaaaaaaaaaaaaaaa x6 : 0000000000000000
[    2.412833] x5 : 0000000000000000 x4 : 0000000000000000
[    2.412834] x3 : 0000000000000000 x2 : ffffffc01005bb84
[    2.412834] x1 : 0000000000002048 x0 : 0000000080000000
[    2.412835] Kernel panic - not syncing: Asynchronous SError Interrupt
[    2.412836] CPU: 6 PID: 1 Comm: swapper/0 Tainted: G S                5.4.22 #103
[    2.412836] Hardware name: Qualcomm Technologies, Inc. SC7180 IDP (DT)
[    2.412836] Call trace:
[    2.412837]  dump_backtrace+0x0/0x150
[    2.412837]  show_stack+0x20/0x2c
[    2.412837]  dump_stack+0xa0/0xd8
[    2.412838]  panic+0x158/0x360
[    2.412838]  panic+0x0/0x360
[    2.412838]  arm64_serror_panic+0x78/0x84
[    2.412839]  do_serror+0x110/0x118
[    2.412839]  el1_error+0x84/0xf8
[    2.412839]  regmap_mmio_read32le+0x28/0x40
[    2.412840]  regmap_mmio_read+0x44/0x6c
[    2.412840]  _regmap_bus_reg_read+0x34/0x44
[    2.412841]  _regmap_read+0x88/0x164
[    2.412841]  regmap_read+0x54/0x78
[    2.412841]  clk_is_enabled_regmap+0x3c/0x8c
[    2.412842]  clk_core_is_enabled+0x68/0xac
[    2.412842]  clk_disable_unused_subtree+0x90/0x22c
[    2.412843]  clk_disable_unused_subtree+0x34/0x22c
[    2.412843]  clk_disable_unused+0x74/0x108
[    2.412843]  do_one_initcall+0x13c/0x2c8
[    2.412844]  do_initcall_level+0x144/0x16c
[    2.412844]  do_basic_setup+0x30/0x48
Quoted 9 lines
[    2.412844]  kernel_init_freeable+0xc4/0x140
[    2.412845]  kernel_init+0x14/0x100
[    2.412845]  ret_from_fork+0x10/0x18
[    2.412858] SMP: stopping secondary CPUs
[    2.412859] Kernel Offset: 0x11e3a00000 from 0xffffffc010000000
[    2.412859] PHYS_OFFSET: 0xffffffe780000000
[    2.412860] CPU features: 0x0006,2a80aa18
[    2.412860] Memory Limit: none
Quoted 4 lines

Hi Matthias,

The display device node is not present and we encounter this crash, would it be possible to add ALWAYS_ON for the MDSS GDSC and give it a try.

It still crashes when ALWAYS_ON is set for the MDSS GDSC.

maintainer
#6 lore raw

Re: [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk

Quoting Matthias Kaehlcke (2020-03-04 09:09:39)

Quoted 10 lines

Hi Taniya,

Quoted 5 lines · Taniya Das

Hi Matthias,

The display device node is not present and we encounter this crash, would it be possible to add ALWAYS_ON for the MDSS GDSC and give it a try.

It still crashes when ALWAYS_ON is set for the MDSS GDSC.

Any updates here? I'm about to send this patch off to Linus and I'm wondering if there will be a resolution besides reverting it.

A message that is not in the archive (sent off-list or not yet received): [email protected]

maintainer
#8 lore raw

Re: [PATCH v1 2/2] clk: qcom: dispcc: Remove support of disp_cc_mdss_rscc_ahb_clk

Quoting Taniya Das (2020-03-14 04:08:47)

Quoted 19 lines

I would require you suggestion on the below.

Quoted 7 lines · Stephen Boyd

Quoting Matthias Kaehlcke (2020-03-04 09:09:39)

Quoted 6 lines

Hi Taniya,

Quoted 3 lines · Taniya Das

Hi Matthias,

Quoted 8 lines
Quoted 4 lines
Quoted 2 lines

The display device node is not present and we encounter this crash, would it be possible to add ALWAYS_ON for the MDSS GDSC and give it a try.

It still crashes when ALWAYS_ON is set for the MDSS GDSC.

Any updates here? I'm about to send this patch off to Linus and I'm wondering if there will be a resolution besides reverting it.

Quoted 9 lines

Looks like the AHB clock needs to be left enabled till the last clocks get disabled. I need to add a new dependency o n this clock.

Hi Stephen,

Any way to keep this dependency using the framework or I need to split the probes to register them independently?

Sorry, I don't understand the problem fully. This AHB clk is left on in the bootloader? Why do we need to touch it if it's always left enabled? Is it actually the case that the bootloader hasn't turned this clk on and we're getting lucky having it marked here as CLK_IS_CRITICAL? Can we force it on in driver probe and then ignore it after that?

maintainer
#9 lore raw
In reply to Taniya Das

Quoting Taniya Das (2020-02-11 04:13:55)

Quoted 15 lines

The clock disable signal for video_cc_vcodec0_core_clk is tied to vcodec0_gdsc which is supported in the HW control mode. Thus turning off the clock would be taken care automatically when the GDSC turns OFF by hardware and clock driver does not require to poll on the CLK_OFF bit.

Signed-off-by Taniya Das <[email protected]>
---
 drivers/clk/qcom/videocc-sc7180.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/qcom/videocc-sc7180.c +0 -0
index c363c3c..276e5ec 100644

drivers/clk/qcom/videocc-sc7180.c static struct clk_branch video_cc_vcodec0_axi_clk = { · line 100

Quoted 5 lines
drivers/clk/qcom/videocc-sc7180.c +1 -1
@@ -97,7 +97,7 @@ static struct clk_branch video_cc_vcodec0_axi_clk = {
 
 static struct clk_branch video_cc_vcodec0_core_clk = {
        .halt_reg = 0x890,
-       .halt_check = BRANCH_HALT,
+       .halt_check = BRANCH_HALT_VOTED,

Ok. I looked closely and now I notice that some code is using BRANCH_VOTED and other code is using BRANCH_HALT_VOTED. In the end, it's the same value. I guess I should remove BRANCH_VOTED from the header file and make it BIT(7) that's ored in there so that everyone consistently uses BRANCH_HALT_VOTED.

Quoted 2 lines
drivers/clk/qcom/videocc-sc7180.c +0 -0
        .clkr = {
                .enable_reg = 0x890,
maintainer Applied
#10 lore raw
In reply to Taniya Das

Quoting Taniya Das (2020-02-11 04:13:55)

Quoted 7 lines

The clock disable signal for video_cc_vcodec0_core_clk is tied to vcodec0_gdsc which is supported in the HW control mode. Thus turning off the clock would be taken care automatically when the GDSC turns OFF by hardware and clock driver does not require to poll on the CLK_OFF bit.

Signed-off-by Taniya Das <[email protected]>

---

Applied to clk-fixes