drm/msm/dpu: add DP support for sc7180 target

index f8ac3bf..136e4d0 100644
@@ -1109,6 +1109,12 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
 	}
 
 	if (dpu_enc->cur_master->hw_mdptop &&
+		(dpu_enc->disp_info.intf_type == DRM_MODE_ENCODER_TMDS) &&
+			dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select)
+		dpu_enc->cur_master->hw_mdptop->ops.intf_audio_select(
+			dpu_enc->cur_master->hw_mdptop);
+
+	if (dpu_enc->cur_master->hw_mdptop &&
 			dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc)
 		dpu_enc->cur_master->hw_mdptop->ops.reset_ubwc(
 				dpu_enc->cur_master->hw_mdptop,

index c567917..60f350f 100644
@@ -109,8 +109,9 @@
 	{
 	.name = "top_0", .id = MDP_TOP,
 	.base = 0x0, .len = 0x494,
-	.features = 0,
+	.features = BIT(DPU_MDP_DP_PHY_SEL),
 	.highest_bank_bit = 0x3,
+	.dp_phy_intf_sel = 0x41,
 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
 		.reg_off = 0x2AC, .bit_off = 0},
 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {

index 09df7d8..fbcf14b 100644
@@ -77,6 +77,7 @@ enum {
  * @DPU_MDP_UBWC_1_0,      This chipsets supports Universal Bandwidth
  *                         compression initial revision
  * @DPU_MDP_UBWC_1_5,      Universal Bandwidth compression version 1.5
+ * @DPU_MDP_DP_PHY_SEL     DP PHY interface select for controller
  * @DPU_MDP_MAX            Maximum value
 
  */

@@ -86,6 +87,7 @@ enum {
 	DPU_MDP_BWC,
 	DPU_MDP_UBWC_1_0,
 	DPU_MDP_UBWC_1_5,
+	DPU_MDP_DP_PHY_SEL,
 	DPU_MDP_MAX
 };
 

@@ -421,6 +423,7 @@ struct dpu_clk_ctrl_reg {
  * @highest_bank_bit:  UBWC parameter
  * @ubwc_static:       ubwc static configuration
  * @ubwc_swizzle:      ubwc default swizzle setting
+ * @dp_phy_intf_sel:   dp phy interface select for controller
  * @clk_ctrls          clock control register definition
  */
 struct dpu_mdp_cfg {

@@ -428,6 +431,7 @@ struct dpu_mdp_cfg {
 	u32 highest_bank_bit;
 	u32 ubwc_static;
 	u32 ubwc_swizzle;
+	u32 dp_phy_intf_sel;
 	struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
 };
 

index efe9a57..ae96ede 100644
@@ -144,10 +144,22 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
 	hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
 	display_hctl = (hsync_end_x << 16) | hsync_start_x;
 
+	if (ctx->cap->type == INTF_DP) {
+		active_h_start = hsync_start_x;
+		active_h_end = active_h_start + p->xres - 1;
+		active_v_start = display_v_start;
+		active_v_end = active_v_start + (p->yres * hsync_period) - 1;
+		active_hctl = (active_h_end << 16) | active_h_start;
+		display_hctl = active_hctl;
+	}
+
 	den_polarity = 0;
 	if (ctx->cap->type == INTF_HDMI) {
 		hsync_polarity = p->yres >= 720 ? 0 : 1;
 		vsync_polarity = p->yres >= 720 ? 0 : 1;
+	} else if (ctx->cap->type == INTF_DP) {
+		hsync_polarity = p->hsync_polarity;
+		vsync_polarity = p->vsync_polarity;
 	} else {
 		hsync_polarity = 0;
 		vsync_polarity = 0;

index f9af52a..9591d42 100644
@@ -41,6 +41,7 @@
 #define MDP_WD_TIMER_4_CTL                0x440
 #define MDP_WD_TIMER_4_CTL2               0x444
 #define MDP_WD_TIMER_4_LOAD_VALUE         0x448
+#define DP_PHY_INTF_SEL                   0x460
 
 #define MDP_TICK_COUNT                    16
 #define XO_CLK_RATE                       19200

@@ -275,6 +276,9 @@ static void dpu_hw_intf_audio_select(struct dpu_hw_mdp *mdp)
 	c = &mdp->hw;
 
 	DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1);
+
+	if (mdp->caps->features & BIT(DPU_MDP_DP_PHY_SEL))
+		DPU_REG_WRITE(c, DP_PHY_INTF_SEL, mdp->caps->dp_phy_intf_sel);
 }
 
 static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,

index 136e4d0..0052212 100644
@@ -1084,6 +1084,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
 
 	dpu_enc->mode_set_complete = true;
 
+	return;
+
 error:
 	dpu_rm_release(&dpu_kms->rm, drm_enc);
 }