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FAILED: patch "[PATCH] drm/i915/gt: Update PMINTRMSK holding fw" failed to apply to 5.6-stable tree

PATCH [email protected] 1 participant 1 message Apr 27, 2020

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Stable branch DRM drivers Intel i915
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The patch below does not apply to the 5.6-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From e1eb075c5051987fbbadbc0fb8211679df657721 Mon Sep 17 00:00:00 2001
From: Chris Wilson <[email protected]>
Date: Wed, 15 Apr 2020 18:03:18 +0100
Subject: [PATCH] drm/i915/gt: Update PMINTRMSK holding fw

If we use a non-forcewaked write to PMINTRMSK, it does not take effect until much later, if at all, causing a loss of RPS interrupts and no GPU reclocking, leaving the GPU running at the wrong frequency for long periods of time.

Reported-by Francisco Jerez <[email protected]>
Suggested-by Francisco Jerez <[email protected]>
Fixes 35cc7f32c298 ("drm/i915/gt: Use non-forcewake writes for RPS")
Signed-off-by Chris Wilson <[email protected]>
Cc Francisco Jerez <[email protected]>
Cc Mika Kuoppala <[email protected]>
Cc Andi Shyti <[email protected]>
Reviewed-by Mika Kuoppala <[email protected]>
Reviewed-by Andi Shyti <[email protected]>
Reviewed-by Francisco Jerez <[email protected]>
Cc <[email protected]> # v5.6+
Link https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit a080bd994c4023042a2b605c65fa10a25933f636)
Signed-off-by Rodrigo Vivi <[email protected]>
drivers/gpu/drm/i915/gt/intel_rps.c +6 -3
index cfaf141bac4d..19542fd9e207 100644
@@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
 		events = (GEN6_PM_RP_UP_THRESHOLD |
 			  GEN6_PM_RP_DOWN_THRESHOLD |
 			  GEN6_PM_RP_DOWN_TIMEOUT);
-
 	WRITE_ONCE(rps->pm_events, events);
+
 	spin_lock_irq(&gt->irq_lock);
 	gen6_gt_pm_enable_irq(gt, rps->pm_events);
 	spin_unlock_irq(&gt->irq_lock);
 
-	set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq));
+	intel_uncore_write(gt->uncore,
+			   GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
 }
 
 static void gen6_rps_reset_interrupts(struct intel_rps *rps)

@@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
 	struct intel_gt *gt = rps_to_gt(rps);
 
 	WRITE_ONCE(rps->pm_events, 0);
-	set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
+
+	intel_uncore_write(gt->uncore,
+			   GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
 
 	spin_lock_irq(&gt->irq_lock);
 	gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);