clk: qcom: Support for Low Power Audio Clocks on SC7180
v3 cover clk: qcom: Support for Low Power Audio Clocks on SC7180
[v3]
* Update the clock-name to iface instead of gcc_lpass_sway.
* Update the documentation with the reg descriptions and use maxItems.
[v2]
* Update retention macro name.
* Update the register description in the documentation.
[v1]
* Add support for Retention of GDSCR.
* Add YAML schema for LPASS clocks and clock IDs for LPASS.
* Add clock driver for LPASS core clocks and GCC LPASS clock.
Taniya Das (4):
clk: qcom: gdsc: Add support to enable retention of GSDCR
dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
clk: qcom: lpass: Add support for LPASS clock controller for SC7180
.../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 98 +++++ drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sc7180.c | 14 + drivers/clk/qcom/gdsc.c | 12 + drivers/clk/qcom/gdsc.h | 1 + drivers/clk/qcom/lpasscorecc-sc7180.c | 478 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 ++ 9 files changed, 643 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml create mode 100644 drivers/clk/qcom/lpasscorecc-sc7180.c create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v3 1/4 clk: qcom: gdsc: Add support to enable retention of GSDCR
Add support for the RETAIN_FF_ENABLE feature which enables the usage of retention registers. These registers maintain their state after disabling and re-enabling a GDSC.
Signed-off-by Taniya Das <[email protected]>
--- drivers/clk/qcom/gdsc.c | 12 ++++++++++++ drivers/clk/qcom/gdsc.h | 1 + 2 files changed, 13 insertions(+)
drivers/clk/qcom/gdsc.c +12 -0
@@ -29,6 +29,7 @@/* CFG_GDSCR */ #define GDSC_POWER_UP_COMPLETE BIT(16)#define GDSC_POWER_DOWN_COMPLETE BIT(15) +#define GDSC_RETAIN_FF_ENABLE BIT(11)#define CFG_GDSCR_OFFSET 0x4/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
@@ -216,6 +217,14 @@ static inline void gdsc_assert_reset_aon(struct gdsc *sc)regmap_update_bits (sc->regmap, sc->clamp_io_ctrl,GMEM_RESET_MASK ,0 ); } + +static void gdsc_retain_ff_on (struct gdsc *sc) +{ +u32 mask =GDSC_RETAIN_FF_ENABLE ; + +regmap_update_bits (sc->regmap, sc->gdscr, mask, mask); +} +static int gdsc_enable (struct generic_pm_domain *domain) {struct gdsc *sc =domain_to_gdsc (domain);
@@ -268,6 +277,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)udelay (1 ); } +if (sc->flags &RETAIN_FF_ENABLE ) +gdsc_retain_ff_on (sc); +return 0 ; }
drivers/clk/qcom/gdsc.h +1 -0
@@ -50,6 +50,7 @@ struct gdsc {#define AON_RESET BIT(4)#define POLL_CFG_GDSCR BIT(5)#define ALWAYS_ON BIT(6) +#define RETAIN_FF_ENABLE BIT(7)struct reset_controller_dev *rcdev;unsigned int *resets;unsigned int reset_count;
Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v3 2/4 dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
In reply to Taniya DasThe LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
Signed-off-by Taniya Das <[email protected]>
--- .../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 98 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 +++++++ 3 files changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +98 -0
@@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7180 + +maintainers: + - Taniya Das <[email protected]> + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h + +properties: + compatible: + enum: + - qcom,sc7180-lpasshm + - qcom,sc7180-lpasscorecc + + clocks: + items: + - description: gcc_lpass_sway clock from GCC + + clock-names: + items: + - const: iface + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 2 + items: + - description: lpass core cc register + - description: lpass audio cc register + + reg-names: + items: + - const: lpass_core_cc + - const: lpass_audio_cc + +if: + properties: + compatible: + contains: + const: qcom,sc7180-lpasshm +then: + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + clock-controller@63000000 { + compatible = "qcom,sc7180-lpasshm"; + reg = <0 0x63000000 0 0x28>; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + clock-controller@62d00000 { + compatible = "qcom,sc7180-lpasscorecc"; + reg = <0 0x62d00000 0 0x50000>, + <0 0x62780000 0 0x30000>; + reg-names = "lpass_core_cc", "lpass_audio_cc"; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "iface"; + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; +...
include/dt-bindings/clock/qcom,gcc-sc7180.h +1 -0
@@ -138,6 +138,7 @@#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128#define GCC_MSS_SNOC_AXI_CLK 129#define GCC_SEC_CTRL_CLK_SRC 130 +#define GCC_LPASS_CFG_NOC_SWAY_CLK 131/* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0
include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h new file +29 -0
@@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H + +/* LPASS_CORE_CC clocks */ +#define LPASS_LPAAUDIO_DIG_PLL 0 +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 +#define CORE_CLK_SRC 2 +#define EXT_MCLK0_CLK_SRC 3 +#define LPAIF_PRI_CLK_SRC 4 +#define LPAIF_SEC_CLK_SRC 5 +#define LPASS_AUDIO_CORE_CORE_CLK 6 +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 + +/* LPASS Core power domains */ +#define LPASS_CORE_HM_GDSCR 0 + +/* LPASS Audio power domains */ +#define LPASS_AUDIO_HM_GDSCR 0 +#define LPASS_PDC_HM_GDSCR 1 + +#endif
Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Rob Herring
maintainerRe: [PATCH v3 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
Quoted 52 lines · Taniya Das
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
Signed-off-by Taniya Das <[email protected]>--- .../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 98 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 +++++++ 3 files changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.hDocumentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +33
-0@@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7180 + +maintainers: + - Taniya Das <[email protected]> + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h + +properties: + compatible: + enum: + - qcom,sc7180-lpasshm + - qcom,sc7180-lpasscorecc + + clocks: + items: + - description: gcc_lpass_sway clock from GCC + + clock-names: + items: + - const: iface + + power-domains:
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml line 43
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +10
-0+ maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 2
You need a 'minItems: 1' here instead.
Quoted 8 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +8
-0+ items: + - description: lpass core cc register + - description: lpass audio cc register + + reg-names: + items: + - const: lpass_core_cc + - const: lpass_audio_cc
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml line 61
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +10
-0+ +if: + properties: + compatible: + contains: + const: qcom,sc7180-lpasshm +then: + properties: + reg: + maxItems: 1
And need an:
else:
properties:
reg:
minItems: 2
Quoted 8 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +8
-0+ +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells'
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml line 79
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +10
-0+ +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + clock-controller@63000000 { + compatible = "qcom,sc7180-lpasshm"; + reg = <0 0x63000000 0 0x28>;
Default sizes are 1 cell.
Quoted 70 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +19
-0+ clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + clock-controller@62d00000 { + compatible = "qcom,sc7180-lpasscorecc"; + reg = <0 0x62d00000 0 0x50000>, + <0 0x62780000 0 0x30000>; + reg-names = "lpass_core_cc", "lpass_audio_cc"; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "iface"; + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; +...include/dt-bindings/clock/qcom,gcc-sc7180.h +1
-0@@ -138,6 +138,7 @@#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128#define GCC_MSS_SNOC_AXI_CLK 129#define GCC_SEC_CTRL_CLK_SRC 130 +#define GCC_LPASS_CFG_NOC_SWAY_CLK 131/* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h new file +29
-0@@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H + +/* LPASS_CORE_CC clocks */ +#define LPASS_LPAAUDIO_DIG_PLL 0 +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 +#define CORE_CLK_SRC 2 +#define EXT_MCLK0_CLK_SRC 3 +#define LPAIF_PRI_CLK_SRC 4 +#define LPAIF_SEC_CLK_SRC 5 +#define LPASS_AUDIO_CORE_CORE_CLK 6 +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 + +/* LPASS Core power domains */ +#define LPASS_CORE_HM_GDSCR 0 + +/* LPASS Audio power domains */ +#define LPASS_AUDIO_HM_GDSCR 0 +#define LPASS_PDC_HM_GDSCR 1 + +#endif Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Re: [PATCH v3 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
Hi Rob,
Thanks for the review.
Quoted 57 lines · Rob Herring
Quoted 56 lines · Taniya Das
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
Signed-off-by Taniya Das <[email protected]>--- .../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 98 ++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 +++++++ 3 files changed, 128 insertions(+)create mode 100644
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yamlcreate mode 100644include/dt-bindings/clock/qcom,lpasscorecc-sc7180.hDocumentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +37
-0@@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7180 + +maintainers: + - Taniya Das <[email protected]> + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h + +properties: + compatible: + enum: + - qcom,sc7180-lpasshm + - qcom,sc7180-lpasscorecc + + clocks: + items: + - description: gcc_lpass_sway clock from GCC + + clock-names: + items: + - const: iface + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1
Quoted 9 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml line 43
Quoted 6 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +6
-0+ + '#power-domain-cells': + const: 1 + + reg: + maxItems: 2You need a 'minItems: 1' here instead.
Will update in the next patch.
Quoted 21 lines
Quoted 8 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +8
-0+ items: + - description: lpass core cc register + - description: lpass audio cc register + + reg-names: + items: + - const: lpass_core_cc + - const: lpass_audio_ccDocumentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml line 61
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +10
-0+ +if: + properties: + compatible: + contains: + const: qcom,sc7180-lpasshm +then: + properties: + reg: + maxItems: 1And need an:
Quoted 4 lines
else:
properties:
reg:
minItems: 2
Will take care of it.
Quoted 13 lines
Quoted 13 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +12
-0+ +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples:
Quoted 8 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml line 79
Quoted 6 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +6
-0+ - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + clock-controller@63000000 { + compatible = "qcom,sc7180-lpasshm"; + reg = <0 0x63000000 0 0x28>;Default sizes are 1 cell.
Yes, my bad, will correct in the next patch.
Quoted 71 lines
Quoted 71 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file +19
-0+ clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + clock-controller@62d00000 { + compatible = "qcom,sc7180-lpasscorecc"; + reg = <0 0x62d00000 0 0x50000>, + <0 0x62780000 0 0x30000>; + reg-names = "lpass_core_cc", "lpass_audio_cc"; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "iface"; + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; +...include/dt-bindings/clock/qcom,gcc-sc7180.h +1
-0@@ -138,6 +138,7 @@#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128#define GCC_MSS_SNOC_AXI_CLK 129#define GCC_SEC_CTRL_CLK_SRC 130 +#define GCC_LPASS_CFG_NOC_SWAY_CLK 131/* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h new file +29
-0@@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* +* Copyright (c) 2020, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H + +/* LPASS_CORE_CC clocks */ +#define LPASS_LPAAUDIO_DIG_PLL 0 +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 +#define CORE_CLK_SRC 2 +#define EXT_MCLK0_CLK_SRC 3 +#define LPAIF_PRI_CLK_SRC 4 +#define LPAIF_SEC_CLK_SRC 5 +#define LPASS_AUDIO_CORE_CORE_CLK 6 +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 + +/* LPASS Core power domains */ +#define LPASS_CORE_HM_GDSCR 0 + +/* LPASS Audio power domains */ +#define LPASS_AUDIO_HM_GDSCR 0 +#define LPASS_PDC_HM_GDSCR 1 + +#endif Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
PATCH v3 3/4 clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
In reply to Taniya DasAdd the GCC lpass clock which is required to access the LPASS core clocks.
Signed-off-by Taniya Das <[email protected]>
--- drivers/clk/qcom/gcc-sc7180.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
drivers/clk/qcom/gcc-sc7180.c +14 -0
@@ -2251,6 +2251,19 @@ static struct clk_branch gcc_mss_q6_memnoc_axi_clk = { }, }; +static struct clk_branch gcc_lpass_cfg_noc_sway_clk = { + .halt_reg =0x47018 , + .halt_check =BRANCH_HALT_DELAY , + .clkr = { + .enable_reg =0x47018 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_lpass_cfg_noc_sway_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct gdsc ufs_phy_gdsc = { .gdscr =0x77004 , .pd = {
@@ -2428,6 +2441,7 @@ static struct clk_regmap *gcc_sc7180_clocks[] = { [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr, [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr, + [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr, };static const struct qcom_reset_map gcc_sc7180_resets[] = {
Signature · 2 lines
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v3 4/4 clk: qcom: lpass: Add support for LPASS clock controller for SC7180
In reply to Taniya DasThe Low Power Audio subsystem clocks are required for Audio client to be able to request for the clocks and power domains.
Signed-off-by Taniya Das <[email protected]>
--- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/lpasscorecc-sc7180.c | 478 ++++++++++++++++++++++++++++++++++ 3 files changed, 488 insertions(+) create mode 100644 drivers/clk/qcom/lpasscorecc-sc7180.c
drivers/clk/qcom/Kconfig +9 -0
@@ -280,6 +280,15 @@ config SC_GCC_7180 Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. +config SC_LPASS_CORECC_7180 + tristate "SC7180 LPASS Core Clock Controller" + select SC_GCC_7180 + help + Support for the LPASS(Low Power Audio Subsystem) core clock controller + on SC7180 devices. + Say Y if you want to use LPASS clocks and power domains of the LPASS + core clock controller. + config SC_GPUCC_7180 tristate "SC7180 Graphics Clock Controller" select SC_GCC_7180
drivers/clk/qcom/Makefile +1 -0
@@ -51,6 +51,7 @@ obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o +obj-$(CONFIG_SC_LPASS_CORECC_7180) += lpasscorecc-sc7180.o obj-$(CONFIG_SC_MSS_7180) += mss-sc7180.o obj-$(CONFIG_SC_VIDEOCC_7180) += videocc-sc7180.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
drivers/clk/qcom/lpasscorecc-sc7180.c new file +478 -0
478 lines not on this page · raw message
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Stephen Boyd
maintainerQuoting Taniya Das (2020-06-10 10:18:03)
Quoted 4 lines
[v3]
* Update the clock-name to iface instead ofgcc_lpass_sway.
* Update the documentation with the reg descriptions and use maxItems.
Most patches look good minus Rob's DT binding comment. Can you resend?