FAILED: patch "[PATCH] drm/i915/gt: Incrementally check for rewinding" failed to apply to 5.4-stable tree
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[email protected]
maintainerThe patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 8ab3a3812aa90e488813e719308ffd807b865624 Mon Sep 17 00:00:00 2001
From: Chris Wilson <[email protected]>
Date: Tue, 9 Jun 2020 16:17:23 +0100
Subject: [PATCH] drm/i915/gt: Incrementally check for rewinding
In commit 5ba32c7be81e ("drm/i915/execlists: Always force a context reload when rewinding RING_TAIL"), we placed the check for rewinding a context on actually submitting the next request in that context. This was so that we only had to check once, and could do so with precision avoiding as many forced restores as possible. For example, to ensure that we can resubmit the same request a couple of times, we include a small wa_tail such that on the next submission, the ring->tail will appear to move forwards when resubmitting the same request. This is very common as it will happen for every lite-restore to fill the second port after a context switch.
However, intel_ring_direction() is limited in precision to movements of upto half the ring size. The consequence being that if we tried to unwind many requests, we could exceed half the ring and flip the sense of the direction, so missing a force restore. As no request can be greater than half the ring (i.e. 2048 bytes in the smallest case), we can check for rollback incrementally. As we check against the tail that would be submitted, we do not lose any sensitivity and allow lite restores for the simple case. We still need to double check upon submitting the context, to allow for multiple preemptions and resubmissions.
drivers/gpu/drm/i915/gt/intel_engine_cs.c +3 -1
@@ -646,7 +646,7 @@ static int engine_setup_common(struct intel_engine_cs *engine)struct measure_breadcrumb {struct i915_request rq;struct intel_ring ring; -u32 cs[1024 ]; +u32 cs[2048 ]; };static int measure_breadcrumb_dw (struct intel_context *ce)
@@ -668,6 +668,8 @@ static int measure_breadcrumb_dw(struct intel_context *ce) frame->ring.vaddr = frame->cs; frame->ring.size =sizeof (frame->cs); + frame->ring.wrap = +BITS_PER_TYPE (frame->ring.size) -ilog2 (frame->ring.size); frame->ring.effective_size = frame->ring.size;intel_ring_update_space (&frame->ring); frame->rq.ring = &frame->ring;
drivers/gpu/drm/i915/gt/intel_lrc.c +20 -1
@@ -1134,6 +1134,13 @@ __unwind_incomplete_requests(struct intel_engine_cs *engine)list_move (&rq->sched.link, pl);set_bit (I915_FENCE_FLAG_PQUEUE , &rq->fence.flags); +/* Check in case we rollback so far we wrap [size/2] */ +if (intel_ring_direction (rq->ring, +intel_ring_wrap (rq->ring, + rq->tail), + rq->ring->tail) >0 ) + rq->context->lrc.desc |=CTX_DESC_FORCE_RESTORE ; + active = rq; }else {struct intel_engine_cs *owner = rq->context->engine;
@@ -1498,8 +1505,9 @@ static u64 execlists_update_context(struct i915_request *rq)* HW has a tendency to ignore us rewinding the TAIL to the end of * an earlier request. */ +GEM_BUG_ON (ce->lrc_reg_state[CTX_RING_TAIL ] != rq->ring->tail); + prev = rq->ring->tail; tail =intel_ring_set_tail (rq->ring, rq->tail); - prev = ce->lrc_reg_state[CTX_RING_TAIL ];if (unlikely (intel_ring_direction (rq->ring, tail, prev) <=0 )) desc |=CTX_DESC_FORCE_RESTORE ; ce->lrc_reg_state[CTX_RING_TAIL ] = tail;
@@ -4758,6 +4766,14 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode)return 0 ; } +static void assert_request_valid (struct i915_request *rq) +{ +struct intel_ring *ring__maybe_unused = rq->ring; + +/* Can we unwind this request without appearing to go forwards? */ +GEM_BUG_ON (intel_ring_direction (ring, rq->wa_tail, rq->head) <=0 ); +} +/* * Reserve space for 2 NOOPs at the end of each request to be * used as a workaround for not being allowed to do lite
@@ -4770,6 +4786,9 @@ static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs) *cs++ =MI_NOOP ; request->wa_tail =intel_ring_offset (request, cs); +/* Check that entire request is less than half the ring */ +assert_request_valid (request); +return cs; }
drivers/gpu/drm/i915/gt/intel_ring.c +4 -0
@@ -315,3 +315,7 @@ int intel_ring_cacheline_align(struct i915_request *rq)GEM_BUG_ON (rq->ring->emit & (CACHELINE_BYTES -1 ));return 0 ; } + +#if IS_ENABLED (CONFIG_DRM_I915_SELFTEST ) +#include "selftest_ring.c" +#endif
drivers/gpu/drm/i915/gt/selftest_mocs.c +16 -2
@@ -18,6 +18,20 @@ struct live_mocs {void *vaddr; }; +static struct intel_context *mocs_context_create (struct intel_engine_cs *engine) +{ +struct intel_context *ce; + + ce =intel_context_create (engine); +if (IS_ERR (ce)) +return ce; + +/* We build large requests to read the registers from the ring */ + ce->ring =__intel_context_ring_size (SZ_16K ); + +return ce; +} +static int request_add_sync (struct i915_request *rq,int err) {i915_request_get (rq);
@@ -301,7 +315,7 @@ static int live_mocs_clean(void *arg)for_each_engine (engine, gt, id) {struct intel_context *ce; - ce =intel_context_create (engine); + ce =mocs_context_create (engine);if (IS_ERR (ce)) { err =PTR_ERR (ce);break ;
@@ -395,7 +409,7 @@ static int live_mocs_reset(void *arg)for_each_engine (engine, gt, id) {struct intel_context *ce; - ce =intel_context_create (engine); + ce =mocs_context_create (engine);if (IS_ERR (ce)) { err =PTR_ERR (ce);break ;
drivers/gpu/drm/i915/gt/selftest_ring.c new file +110 -0
110 lines not on this page · raw message
drivers/gpu/drm/i915/selftests/i915_mock_selftests.h +1 -0
@@ -21,6 +21,7 @@ selftest(fence, i915_sw_fence_mock_selftests) selftest(scatterlist, scatterlist_mock_selftests) selftest(syncmap, i915_syncmap_mock_selftests) selftest(uncore, intel_uncore_mock_selftests) +selftest(ring, intel_ring_mock_selftests) selftest(engine, intel_engine_cs_mock_selftests) selftest(timelines, intel_timeline_mock_selftests)selftest (requests, i915_request_mock_selftests)