FAILED: patch "[PATCH] drm/i915/gt: Move ivb GT workarounds from init_clock_gating" failed to apply to 5.4-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 7237b190add0794bd95979018a23eda698f2705d Mon Sep 17 00:00:00 2001
From: Chris Wilson <[email protected]>
Date: Thu, 11 Jun 2020 09:01:36 +0100
Subject: [PATCH] drm/i915/gt: Move ivb GT workarounds from init_clock_gating
to workarounds
Rescue the GT workarounds from being buried inside init_clock_gating so that we remember to apply them after a GT reset, and that they are included in our verification that the workarounds are applied.
Signed-off-by Chris Wilson <[email protected]>
Reviewed-by Mika Kuoppala <[email protected]>
(cherry picked from commit 19f1f627b33385a2f0855cbc7d33d86d7f4a1e78)
Signed-off-by Joonas Lahtinen <[email protected]>
drivers/gpu/drm/i915/gt/intel_workarounds.c +62 -0
@@ -692,6 +692,66 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)return 0 ; } +static void +ivb_gt_workarounds_init (struct drm_i915_private *i915,struct i915_wa_list *wal) +{ +/* WaDisableEarlyCull:ivb */ +wa_masked_en (wal, _3D_CHICKEN3, _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); + +/* WaDisablePSDDualDispatchEnable:ivb */ +if (IS_IVB_GT1 (i915)) +wa_masked_en (wal, +GEN7_HALF_SLICE_CHICKEN1 , +GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE ); + +/* WaDisable_RenderCache_OperationalFlush:ivb */ +wa_masked_dis (wal,CACHE_MODE_0_GEN7 ,RC_OP_FLUSH_ENABLE ); + +/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ +wa_masked_dis (wal, +GEN7_COMMON_SLICE_CHICKEN1 , +GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ); + +/* WaApplyL3ControlAndL3ChickenMode:ivb */ +wa_write (wal,GEN7_L3CNTLREG1 ,GEN7_WA_FOR_GEN7_L3_CONTROL ); +wa_write (wal,GEN7_L3_CHICKEN_MODE_REGISTER ,GEN7_WA_L3_CHICKEN_MODE ); + +/* WaForceL3Serialization:ivb */ +wa_write_clr (wal,GEN7_L3SQCREG4 ,L3SQ_URB_READ_CAM_MATCH_DISABLE ); + +/* +* WaVSThreadDispatchOverride:ivb,vlv +* +* This actually overrides the dispatch +* mode for all thread types. +*/ +wa_write_masked_or (wal,GEN7_FF_THREAD_MODE , +GEN7_FF_SCHED_MASK , +GEN7_FF_TS_SCHED_HW | +GEN7_FF_VS_SCHED_HW | +GEN7_FF_DS_SCHED_HW ); + +if (0 ) {/* causes HiZ corruption on ivb:gt1 */ +/* enable HiZ Raw Stall Optimization */ +wa_masked_dis (wal,CACHE_MODE_0_GEN7 ,HIZ_RAW_STALL_OPT_DISABLE ); + } + +/* WaDisable4x2SubspanOptimization:ivb */ +wa_masked_en (wal,CACHE_MODE_1 ,PIXEL_SUBSPAN_COLLECT_OPT_DISABLE ); + +/* +* BSpec recommends 8x4 when MSAA is used, +* however in practice 16x4 seems fastest. +* +* Note that PS/WM thread counts depend on the WIZ hashing +* disable bit, which we don't touch here, but it's good +* to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). +*/ +wa_add (wal,GEN7_GT_MODE ,0 , +_MASKED_FIELD (GEN6_WIZ_HASHING_MASK , GEN6_WIZ_HASHING_16x4), + GEN6_WIZ_HASHING_16x4); +} +static void hsw_gt_workarounds_init (struct drm_i915_private *i915,struct i915_wa_list *wal) {
@@ -1011,6 +1071,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)skl_gt_workarounds_init (i915, wal); else if (IS_HASWELL(i915)) hsw_gt_workarounds_init(i915, wal); + else if (IS_IVYBRIDGE(i915)) + ivb_gt_workarounds_init(i915, wal); else if (INTEL_GEN(i915) <= 8) return; else
drivers/gpu/drm/i915/i915_reg.h +1 -1
@@ -7896,7 +7896,7 @@ enum {/* GEN7 chicken */ #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) -#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1 << 10) | (1 << 26)) +#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)#define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
drivers/gpu/drm/i915/intel_pm.c +0 -48
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