arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver
Subsystems (4)
PATCH v3 1/1 arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver
From: Ajit Pandey <[email protected]>
Add the I2S controller node to sc7180 dtsi.
Add pinmux for primary and secondary I2S.
---
Changes since v1:
-- Updated I2S pin control nodes with grouping common pin controls -- Updated lpass_cpu node with proper control names
Changes since v2:
-- The plement of lpass_cpu node is changed
arch/arm64/boot/dts/qcom/sc7180.dtsi | 69 ++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +69 -0
@@ -1742,6 +1742,45 @@ }; }; + sec_mi2s_active: sec-mi2s-active { + pinmux { + pins = "gpio49", "gpio50", "gpio51"; + function = "mi2s_1"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51";; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_active: pri-mi2s-active { + pinmux { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "mi2s_0"; + }; + + pinconf { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_mclk_active: pri-mi2s-mclk-active { + pinmux { + pins = "gpio57"; + function = "lpass_ext"; + }; + + pinconf { + pins = "gpio57"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc1_on: sdc1-on { pinconf-clk { pins = "sdc1_clk";
@@ -3389,6 +3428,36 @@ #power-domain-cells = <1>; }; + lpass_cpu: lpass@62f00000 { + compatible = "qcom,sc7180-lpass-cpu"; + + reg = <0 0x62f00000 0 0x29000>; + reg-names = "lpass-lpaif"; + + iommus = <&apps_smmu 0x1020 0>; + + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, + <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, + <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; + + clock-names = "pcnoc-sway-clk", "audio-core", + "mclk0", "pcnoc-mport-clk", + "mi2s-bit-clk0", "mi2s-bit-clk1"; + + + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpass-irq-lpaif"; + }; + lpass_hm: clock-controller@63000000 { compatible = "qcom,sc7180-lpasshm"; reg = <0 0x63000000 0 0x28>;
Signature · 2 lines
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
Hi,
Quoted 5 lines · Srinivasa Rao Mandadapu
arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0@@ -1742,6 +1742,45 @@ };
arch/arm64/boot/dts/qcom/sc7180.dtsi line 1752
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +8
-0}; + sec_mi2s_active: sec-mi2s-active { + pinmux { + pins = "gpio49", "gpio50", "gpio51"; + function = "mi2s_1"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51";;
There are still two ";" on the above line.
Thanks Mr. Doug for Review comments!!
Quoted 10 lines · Doug Anderson
Hi,
Quoted 6 lines · Srinivasa Rao Mandadapu
arch/arm64/boot/dts/qcom/sc7180.dtsi +0
-0@@ -1742,6 +1742,45 @@ }; };
Quoted 9 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi line 1752
Quoted 8 lines
arch/arm64/boot/dts/qcom/sc7180.dtsi +8
-0+ sec_mi2s_active: sec-mi2s-active { + pinmux { + pins = "gpio49", "gpio50", "gpio51"; + function = "mi2s_1"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51";;There are still two ";" on the above line.
will fix this type error.
Signature · 2 lines
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
Quoted 9 lines · Srinivasa Rao Mandadapu
From: Ajit Pandey <[email protected]>
Add the I2S controller node to sc7180 dtsi.
Add pinmux for primary and secondary I2S.Signed-off-by Ajit Pandey <[email protected]>Signed-off-by Cheng-Yi Chiang <[email protected]>Signed-off-by Srinivasa Rao Mandadapu <[email protected]>Signed-off-by V Sujith Kumar Reddy <[email protected]>
Each s-o-b is a statement that this patch conforms to the license requirements of the Linux project. As such it describes the history of how this patch reached this point; starting with Ajit writing the patch, Cheng-Yi handling it, then you and finally Sujith.
You sending the patch would indicate that you handled it last, so your certification should be last (and if Sujith handled the patch inbetween you should be listed twice).
Regards,
Bjorn
Quoted 101 lines
---
Changes since v1:
-- Updated I2S pin control nodes with grouping common pin controls -- Updatedlpass_cpunode with proper control names
Changes since v2:
-- The plement oflpass_cpunode is changedarch/arm64/boot/dts/qcom/sc7180.dtsi | 69 ++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+)arch/arm64/boot/dts/qcom/sc7180.dtsi +69
-0@@ -1742,6 +1742,45 @@ }; }; + sec_mi2s_active: sec-mi2s-active { + pinmux { + pins = "gpio49", "gpio50", "gpio51"; + function = "mi2s_1"; + }; + + pinconf { + pins = "gpio49", "gpio50", "gpio51";; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_active: pri-mi2s-active { + pinmux { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + function = "mi2s_0"; + }; + + pinconf { + pins = "gpio53", "gpio54", "gpio55", "gpio56"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_mclk_active: pri-mi2s-mclk-active { + pinmux { + pins = "gpio57"; + function = "lpass_ext"; + }; + + pinconf { + pins = "gpio57"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc1_on: sdc1-on { pinconf-clk { pins = "sdc1_clk";@@ -3389,6 +3428,36 @@ #power-domain-cells = <1>; }; + lpass_cpu: lpass@62f00000 { + compatible = "qcom,sc7180-lpass-cpu"; + + reg = <0 0x62f00000 0 0x29000>; + reg-names = "lpass-lpaif"; + + iommus = <&apps_smmu 0x1020 0>; + + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, + <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, + <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; + + clock-names = "pcnoc-sway-clk", "audio-core", + "mclk0", "pcnoc-mport-clk", + "mi2s-bit-clk0", "mi2s-bit-clk1"; + + + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpass-irq-lpaif"; + }; + lpass_hm: clock-controller@63000000 { compatible = "qcom,sc7180-lpasshm"; reg = <0 0x63000000 0 0x28>;Signature · 2 lines
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.