Add Camera clock controller driver for SC7180
v2 cover Add Camera clock controller driver for SC7180
[v2]
* Update PLL set rate function : clk_alpha_pll_agera_set_rate
* Remove mb()
[v1]
* Add support for Agera PLL which is used in the camera clock controller.
* Add driver support for camera clock controller for SC7180 and also update device tree bindings for the various clocks supported in the clock controller.
Taniya Das (3):
clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
dt-bindings: clock: Add YAML schemas for the QCOM Camera clock
bindings.
clk: qcom: camcc: Add camera clock controller driver for SC7180
.../bindings/clock/qcom,sc7180-camcc.yaml | 73 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-sc7180.c | 1737 ++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.c | 80 + drivers/clk/qcom/clk-alpha-pll.h | 4 + include/dt-bindings/clock/qcom,camcc-sc7180.h | 121 ++ 7 files changed, 2025 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml create mode 100644 drivers/clk/qcom/camcc-sc7180.c create mode 100644 include/dt-bindings/clock/qcom,camcc-sc7180.h
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v2 1/3 clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
Add programming sequence support for managing the Agera PLLs.
--- drivers/clk/qcom/clk-alpha-pll.c | 80 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 4 ++ 2 files changed, 84 insertions(+)
drivers/clk/qcom/clk-alpha-pll.c +80 -0
@@ -116,6 +116,16 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_OPMODE] = 0x38, [PLL_OFF_ALPHA_VAL] = 0x40, }, + [CLK_ALPHA_PLL_TYPE_AGERA] = { + [PLL_OFF_L_VAL] = 0x04, + [PLL_OFF_ALPHA_VAL] = 0x08, + [PLL_OFF_USER_CTL] = 0x0c, + [PLL_OFF_CONFIG_CTL] = 0x10, + [PLL_OFF_CONFIG_CTL_U] = 0x14, + [PLL_OFF_TEST_CTL] = 0x18, + [PLL_OFF_TEST_CTL_U] = 0x1c, + [PLL_OFF_STATUS] = 0x2c, + }, };EXPORT_SYMBOL_GPL (clk_alpha_pll_regs);
@@ -1561,3 +1571,73 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, };EXPORT_SYMBOL_GPL (clk_alpha_pll_postdiv_lucid_ops); + +void clk_agera_pll_configure (struct clk_alpha_pll *pll,struct regmap *regmap, +const struct alpha_pll_config *config) +{ +if (config->l) +regmap_write (regmap,PLL_L_VAL (pll), config->l); + +if (config->alpha) +regmap_write (regmap,PLL_ALPHA_VAL (pll), config->alpha); + +if (config->user_ctl_val) +regmap_write (regmap,PLL_USER_CTL (pll), config->user_ctl_val); + +if (config->config_ctl_val) +regmap_write (regmap,PLL_CONFIG_CTL (pll), + config->config_ctl_val); + +if (config->config_ctl_hi_val) +regmap_write (regmap,PLL_CONFIG_CTL_U (pll), + config->config_ctl_hi_val); + +if (config->test_ctl_val) +regmap_write (regmap,PLL_TEST_CTL (pll), + config->test_ctl_val); + +if (config->test_ctl_hi_val) +regmap_write (regmap,PLL_TEST_CTL_U (pll), + config->test_ctl_hi_val); +} +EXPORT_SYMBOL_GPL (clk_agera_pll_configure); + +static int clk_alpha_pll_agera_set_rate (struct clk_hw *hw,unsigned long rate, +unsigned long prate) +{ +struct clk_alpha_pll *pll =to_clk_alpha_pll (hw); +u32 l, alpha_width =pll_alpha_width (pll); +unsigned long rrate, max = rate +PLL_RATE_MARGIN ; +u64 a; + + rrate =alpha_pll_round_rate (rate, prate, &l, &a, alpha_width); + +/* +* Due to limited number of bits for fractional rate programming, the +* rounded up rate could be marginally higher than the requested rate. +*/ +if (rrate > (rate +PLL_RATE_MARGIN ) || rrate < rate) { +pr_err ("%s: Rounded rate %lu not within range [%lu, %lu)\n" , +clk_hw_get_name (hw), rrate, rate, max); +return -EINVAL ; + } + +/* change L_VAL without having to go through the power on sequence */ +regmap_write (pll->clkr.regmap,PLL_L_VAL (pll), l); +regmap_write (pll->clkr.regmap,PLL_ALPHA_VAL (pll), a); + +if (clk_hw_is_enabled (hw)) +return wait_for_pll_enable_lock (pll); + +return 0 ; +} + +const struct clk_ops clk_alpha_pll_agera_ops = { + .enable = clk_alpha_pll_enable, + .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, + .recalc_rate = alpha_pll_fabia_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = clk_alpha_pll_agera_set_rate, +}; +EXPORT_SYMBOL_GPL (clk_alpha_pll_agera_ops);
drivers/clk/qcom/clk-alpha-pll.h +4 -0
@@ -15,6 +15,7 @@ enum {CLK_ALPHA_PLL_TYPE_FABIA ,CLK_ALPHA_PLL_TYPE_TRION ,CLK_ALPHA_PLL_TYPE_LUCID =CLK_ALPHA_PLL_TYPE_TRION , +CLK_ALPHA_PLL_TYPE_AGERA , CLK_ALPHA_PLL_TYPE_MAX, };
@@ -141,6 +142,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;extern const struct clk_ops clk_alpha_pll_lucid_ops;#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_opsextern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; +extern const struct clk_ops clk_alpha_pll_agera_ops;void clk_alpha_pll_configure (struct clk_alpha_pll *pll,struct regmap *regmap,const struct alpha_pll_config *config);
@@ -148,6 +150,8 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, const struct alpha_pll_config *config);void clk_trion_pll_configure (struct clk_alpha_pll *pll,struct regmap *regmap,const struct alpha_pll_config *config); +void clk_agera_pll_configure (struct clk_alpha_pll *pll,struct regmap *regmap, +const struct alpha_pll_config *config);#define clk_lucid_pll_configure (pll, regmap, config) \ clk_trion_pll_configure(pll, regmap, config)
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Stephen Boyd
maintainerRe: [PATCH v2 1/3] clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
Quoting Taniya Das (2020-10-13 10:11:48)
Quoted 5 lines
drivers/clk/qcom/clk-alpha-pll.c +0
-0
drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1579
Quoted 9 lines
drivers/clk/qcom/clk-alpha-pll.c +6
-0@@ -1561,3 +1571,73 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, };EXPORT_SYMBOL_GPL (clk_alpha_pll_postdiv_lucid_ops); + +void clk_agera_pll_configure (struct clk_alpha_pll *pll,struct regmap *regmap, +const struct alpha_pll_config *config) +{ +if (config->l) +regmap_write (regmap,PLL_L_VAL (pll), config->l);
Maybe make a helper function for this too. That way we can't mix up the if condition with the value in the write.
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
static void clk_alpha_pll_write_config(struct regmap *regmap,
unsigned int reg,
unsigned int val) {
if (val)
regmap_write(regmap, reg, val);
}and how are we so lucky that zero isn't a value that we may need to write?
Quoted 34 lines
drivers/clk/qcom/clk-alpha-pll.c +34
-0+ +if (config->alpha) +regmap_write (regmap,PLL_ALPHA_VAL (pll), config->alpha); + +if (config->user_ctl_val) +regmap_write (regmap,PLL_USER_CTL (pll), config->user_ctl_val); + +if (config->config_ctl_val) +regmap_write (regmap,PLL_CONFIG_CTL (pll), + config->config_ctl_val); + +if (config->config_ctl_hi_val) +regmap_write (regmap,PLL_CONFIG_CTL_U (pll), + config->config_ctl_hi_val); + +if (config->test_ctl_val) +regmap_write (regmap,PLL_TEST_CTL (pll), + config->test_ctl_val); + +if (config->test_ctl_hi_val) +regmap_write (regmap,PLL_TEST_CTL_U (pll), + config->test_ctl_hi_val); +} +EXPORT_SYMBOL_GPL (clk_agera_pll_configure); + +static int clk_alpha_pll_agera_set_rate (struct clk_hw *hw,unsigned long rate, +unsigned long prate) +{ +struct clk_alpha_pll *pll =to_clk_alpha_pll (hw); +u32 l, alpha_width =pll_alpha_width (pll); +unsigned long rrate, max = rate +PLL_RATE_MARGIN ; +u64 a; + + rrate =alpha_pll_round_rate (rate, prate, &l, &a, alpha_width);
drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1623
Quoted 10 lines
drivers/clk/qcom/clk-alpha-pll.c +10
-0+ +/* +* Due to limited number of bits for fractional rate programming, the +* rounded up rate could be marginally higher than the requested rate. +*/ +if (rrate > (rate +PLL_RATE_MARGIN ) || rrate < rate) { +pr_err ("%s: Rounded rate %lu not within range [%lu, %lu)\n" , +clk_hw_get_name (hw), rrate, rate, max); +return -EINVAL ; + }
Can this be extracted into a helper function?
Quoted 11 lines
drivers/clk/qcom/clk-alpha-pll.c +11
-0+ +/* change L_VAL without having to go through the power on sequence */ +regmap_write (pll->clkr.regmap,PLL_L_VAL (pll), l); +regmap_write (pll->clkr.regmap,PLL_ALPHA_VAL (pll), a); + +if (clk_hw_is_enabled (hw)) +return wait_for_pll_enable_lock (pll); + +return 0 ; +} +
Re: [PATCH v2 1/3] clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
Thanks Stephen for the review comments.
Quoted 10 lines · Stephen Boyd
Quoting Taniya Das (2020-10-13 10:11:48)
Quoted 9 lines
drivers/clk/qcom/clk-alpha-pll.c +1
-0@@ -1561,3 +1571,73 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, };EXPORT_SYMBOL_GPL (clk_alpha_pll_postdiv_lucid_ops); +
Quoted 9 lines
drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1579
Quoted 5 lines
drivers/clk/qcom/clk-alpha-pll.c +5
-0+void clk_agera_pll_configure (struct clk_alpha_pll *pll,struct regmap *regmap, +const struct alpha_pll_config *config) +{ +if (config->l) +regmap_write (regmap,PLL_L_VAL (pll), config->l);Maybe make a helper function for this too. That way we can't mix up the if condition with the value in the write.
Sure, I will add a helper function.
Quoted 50 lines
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);static void clk_alpha_pll_write_config(struct regmap *regmap,
unsigned int reg, unsigned int val) { if (val) regmap_write(regmap, reg, val); }and how are we so lucky that zero isn't a value that we may need to write?
Quoted 38 lines
drivers/clk/qcom/clk-alpha-pll.c +38
-0+ +if (config->alpha) +regmap_write (regmap,PLL_ALPHA_VAL (pll), config->alpha); + +if (config->user_ctl_val) +regmap_write (regmap,PLL_USER_CTL (pll), config->user_ctl_val); + +if (config->config_ctl_val) +regmap_write (regmap,PLL_CONFIG_CTL (pll), + config->config_ctl_val); + +if (config->config_ctl_hi_val) +regmap_write (regmap,PLL_CONFIG_CTL_U (pll), + config->config_ctl_hi_val); + +if (config->test_ctl_val) +regmap_write (regmap,PLL_TEST_CTL (pll), + config->test_ctl_val); + +if (config->test_ctl_hi_val) +regmap_write (regmap,PLL_TEST_CTL_U (pll), + config->test_ctl_hi_val); +} +EXPORT_SYMBOL_GPL (clk_agera_pll_configure); + +static int clk_alpha_pll_agera_set_rate (struct clk_hw *hw,unsigned long rate, +unsigned long prate) +{ +struct clk_alpha_pll *pll =to_clk_alpha_pll (hw); +u32 l, alpha_width =pll_alpha_width (pll); +unsigned long rrate, max = rate +PLL_RATE_MARGIN ; +u64 a; + + rrate =alpha_pll_round_rate (rate, prate, &l, &a, alpha_width); + +/* +* Due to limited number of bits for fractional rate programming, the +* rounded up rate could be marginally higher than the requested rate.
Quoted 9 lines
drivers/clk/qcom/clk-alpha-pll.c const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { · line 1623
Quoted 6 lines
drivers/clk/qcom/clk-alpha-pll.c +6
-0+*/ +if (rrate > (rate +PLL_RATE_MARGIN ) || rrate < rate) { +pr_err ("%s: Rounded rate %lu not within range [%lu, %lu)\n" , +clk_hw_get_name (hw), rrate, rate, max); +return -EINVAL ; + }Can this be extracted into a helper function?
Yes, I will add this too.
Quoted 11 lines
Quoted 11 lines
drivers/clk/qcom/clk-alpha-pll.c +11
-0+ +/* change L_VAL without having to go through the power on sequence */ +regmap_write (pll->clkr.regmap,PLL_L_VAL (pll), l); +regmap_write (pll->clkr.regmap,PLL_ALPHA_VAL (pll), a); + +if (clk_hw_is_enabled (hw)) +return wait_for_pll_enable_lock (pll); + +return 0 ; +} +
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
PATCH v2 2/3 dt-bindings: clock: Add YAML schemas for the QCOM Camera clock bindings.
In reply to Taniya DasThe Camera Subsystem clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those.
Add clock ids for camera clocks which are required to bring the camera subsystem out of reset.
--- .../bindings/clock/qcom,sc7180-camcc.yaml | 73 +++++++++++++ include/dt-bindings/clock/qcom,camcc-sc7180.h | 121 +++++++++++++++++++++ 2 files changed, 194 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml create mode 100644 include/dt-bindings/clock/qcom,camcc-sc7180.h
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml new file +73 -0
@@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller Binding for SC7180 + +maintainers: + - Taniya Das <[email protected]> + +description: | + Qualcomm camera clock control module which supports the clocks, resets and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,camcc-sc7180.h. + +properties: + compatible: + const: qcom,sc7180-camcc + + clocks: + items: + - description: Board XO source + - description: Camera_ahb clock from GCC + - description: Camera XO clock from GCC + + clock-names: + items: + - const: bi_tcxo + - const: iface + - const: xo + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@ad00000 { + compatible = "qcom,sc7180-camcc"; + reg = <0x0ad00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_XO_CLK>; + clock-names = "bi_tcxo", "iface", "xo"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +...
include/dt-bindings/clock/qcom,camcc-sc7180.h new file +121 -0
121 lines not on this page · raw message
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Stephen Boyd
maintainerRe: [PATCH v2 2/3] dt-bindings: clock: Add YAML schemas for the QCOM Camera clock bindings.
Quoting Taniya Das (2020-10-13 10:11:49)
Quoted 13 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml new file +7
-0@@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller Binding for SC7180
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml line 17
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml new file +10
-0+ +maintainers: + - Taniya Das <[email protected]> + +description: | + Qualcomm camera clock control module which supports the clocks, resets and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,camcc-sc7180.h.
Maybe just
- dt-bindings/clock/qcom,camcc-sc7180.h
so that us copy/pasters don't have to delete anything.
Quoted 11 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml new file +11
-0+ +properties: + compatible: + const: qcom,sc7180-camcc + + clocks: + items: + - description: Board XO source + - description: Camera_ahb clock from GCC + - description: Camera XO clock from GCC +
Re: [PATCH v2 2/3] dt-bindings: clock: Add YAML schemas for the QCOM Camera clock bindings.
Thanks for your review Stephen.
Quoted 27 lines · Stephen Boyd
Quoting Taniya Das (2020-10-13 10:11:49)
Quoted 13 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml new file +7
-0@@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller Binding for SC7180Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml line 17
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml new file +10
-0+ +maintainers: + - Taniya Das <[email protected]> + +description: | + Qualcomm camera clock control module which supports the clocks, resets and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,camcc-sc7180.h.Maybe just
Quoted 4 lines
-
dt-bindings/clock/qcom,camcc-sc7180.hso that us copy/pasters don't have to delete anything.
Will be fixed in the next patch.
Quoted 11 lines
Quoted 11 lines
Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml new file +11
-0+ +properties: + compatible: + const: qcom,sc7180-camcc + + clocks: + items: + - description: Board XO source + - description: Camera_ahb clock from GCC + - description: Camera XO clock from GCC +
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
Re: [PATCH v2 2/3] dt-bindings: clock: Add YAML schemas for the QCOM Camera clock bindings.
In reply to Taniya DasQuoted 6 lines · Taniya Das
The Camera Subsystem clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those.
Add clock ids for camera clocks which are required to bring the camera subsystem out of reset.
Quoted 8 lines
Signed-off-by Taniya Das <[email protected]>--- .../bindings/clock/qcom,sc7180-camcc.yaml | 73 +++++++++++++ include/dt-bindings/clock/qcom,camcc-sc7180.h | 121 +++++++++++++++++++++ 2 files changed, 194 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml create mode 100644 include/dt-bindings/clock/qcom,camcc-sc7180.h
PATCH v2 3/3 clk: qcom: camcc: Add camera clock controller driver for SC7180
In reply to Taniya DasAdd support for the camera clock controller found on SC7180 based devices. This would allow camera drivers to probe and control their clocks.
--- drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/camcc-sc7180.c | 1737 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 1747 insertions(+) create mode 100644 drivers/clk/qcom/camcc-sc7180.c
drivers/clk/qcom/Kconfig +9 -0
@@ -290,6 +290,15 @@ config QCS_GCC_404 Say Y if you want to use multimedia devices or peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc. +config SC_CAMCC_7180 + tristate "SC7180 Camera Clock Controller" + select SC_GCC_7180 + help + Support for the camera clock controller on Qualcomm Technologies, Inc + SC7180 devices. + Say Y if you want to support camera devices and functionality such as + capturing pictures. + config SC_DISPCC_7180 tristate "SC7180 Display Clock Controller" select SC_GCC_7180
drivers/clk/qcom/Makefile +1 -0
@@ -51,6 +51,7 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o +obj-$(CONFIG_SC_CAMCC_7180) += camcc-sc7180.o obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o
drivers/clk/qcom/camcc-sc7180.c new file +1737 -0
1,737 lines not on this page · raw message
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Stephen Boyd
maintainerRe: [PATCH v2 3/3] clk: qcom: camcc: Add camera clock controller driver for SC7180
Quoting Taniya Das (2020-10-13 10:11:50)
Quoted 6 lines
drivers/clk/qcom/camcc-sc7180.c new file +0
-0@@ -0,0 +1,1737 @@
[...]
drivers/clk/qcom/camcc-sc7180.c line 35
Quoted 12 lines
drivers/clk/qcom/camcc-sc7180.c new file +12
-0+ +enum { +P_BI_TCXO , +P_CAM_CC_PLL0_OUT_EVEN , +P_CAM_CC_PLL1_OUT_EVEN , +P_CAM_CC_PLL2_OUT_AUX , +P_CAM_CC_PLL2_OUT_EARLY , +P_CAM_CC_PLL3_OUT_MAIN , +P_CORE_BI_PLL_TEST_SE , +}; + +static struct pll_vco agera_vco[] = {
Can this be const?
drivers/clk/qcom/camcc-sc7180.c line 39
Quoted 4 lines
drivers/clk/qcom/camcc-sc7180.c new file +4
-0+ { 600000000, 3300000000, 0 }, +}; + +static struct pll_vco fabia_vco[] = {
Can this be const?
Quoted 3 lines
drivers/clk/qcom/camcc-sc7180.c new file +3
-0+ { 249600000, 2000000000, 0 }, +}; +
[...]
Quoted 34 lines
drivers/clk/qcom/camcc-sc7180.c new file +34
-0+ +static int cam_cc_sc7180_probe (struct platform_device *pdev) +{ +struct regmap *regmap; +int ret; + +pm_runtime_enable (&pdev->dev); + ret =pm_clk_create (&pdev->dev); +if (ret) +return ret; + + ret =pm_clk_add (&pdev->dev,"xo" ); +if (ret <0 ) { +dev_err (&pdev->dev,"Failed to acquire XO clock\n" ); + goto disable_pm_runtime; + } + + ret =pm_clk_add (&pdev->dev,"iface" ); +if (ret <0 ) { +dev_err (&pdev->dev,"Failed to acquire iface clock\n" ); + goto disable_pm_runtime; + } + + ret =pm_clk_runtime_resume (&pdev->dev); +if (ret) { +dev_err (&pdev->dev,"pm runtime resume failed\n" ); + goto destroy_pm_clk; + } + + regmap =qcom_cc_map (pdev, &cam_cc_sc7180_desc); +if (IS_ERR (regmap)) { + ret =PTR_ERR (regmap); + goto destroy_pm_clk; + }
drivers/clk/qcom/camcc-sc7180.c line 1692
Quoted 10 lines
drivers/clk/qcom/camcc-sc7180.c new file +10
-0+ +clk_fabia_pll_configure (&cam_cc_pll0, regmap, &cam_cc_pll0_config); +clk_fabia_pll_configure (&cam_cc_pll1, regmap, &cam_cc_pll1_config); +clk_agera_pll_configure (&cam_cc_pll2, regmap, &cam_cc_pll2_config); +clk_fabia_pll_configure (&cam_cc_pll3, regmap, &cam_cc_pll3_config); + + ret =qcom_cc_really_probe (pdev, &cam_cc_sc7180_desc, regmap); +if (ret) { +dev_err (&pdev->dev,"Failed to register CAM CC clocks\n" ); + goto suspend_pm_runtime;
ret is non-zero here
drivers/clk/qcom/camcc-sc7180.c line 1696
Quoted 4 lines
drivers/clk/qcom/camcc-sc7180.c new file +4
-0+ } + +suspend_pm_runtime: + ret =pm_clk_runtime_suspend (&pdev->dev);
But then it is overwritten here.
drivers/clk/qcom/camcc-sc7180.c line 1700
Quoted 4 lines
drivers/clk/qcom/camcc-sc7180.c new file +4
-0+if (ret) +dev_err (&pdev->dev,"pm runtime suspend failed\n" ); + +return 0 ;
And we return 0 when there was a failure to probe the clks?
Quoted 9 lines
drivers/clk/qcom/camcc-sc7180.c new file +9
-0+ +destroy_pm_clk: +pm_clk_destroy (&pdev->dev); + +disable_pm_runtime: +pm_runtime_disable (&pdev->dev); + +return ret; +}
Re: [PATCH v2 3/3] clk: qcom: camcc: Add camera clock controller driver for SC7180
Thanks for your review Stephen.
Quoted 30 lines · Stephen Boyd
Quoting Taniya Das (2020-10-13 10:11:50)
Quoted 6 lines
drivers/clk/qcom/camcc-sc7180.c new file +0
-0@@ -0,0 +1,1737 @@[...]
drivers/clk/qcom/camcc-sc7180.c line 35
Quoted 12 lines
drivers/clk/qcom/camcc-sc7180.c new file +12
-0+ +enum { +P_BI_TCXO , +P_CAM_CC_PLL0_OUT_EVEN , +P_CAM_CC_PLL1_OUT_EVEN , +P_CAM_CC_PLL2_OUT_AUX , +P_CAM_CC_PLL2_OUT_EARLY , +P_CAM_CC_PLL3_OUT_MAIN , +P_CORE_BI_PLL_TEST_SE , +}; + +static struct pll_vco agera_vco[] = {Can this be const?
drivers/clk/qcom/camcc-sc7180.c line 39
Quoted 4 lines
drivers/clk/qcom/camcc-sc7180.c new file +4
-0+ { 600000000, 3300000000, 0 }, +}; + +static struct pll_vco fabia_vco[] = {Can this be const?
Quoted 4 lines
Quoted 3 lines
drivers/clk/qcom/camcc-sc7180.c new file +3
-0+ { 249600000, 2000000000, 0 }, +}; +[...]
Will take care of the above in the next patch.
Quoted 54 lines
Quoted 34 lines
drivers/clk/qcom/camcc-sc7180.c new file +34
-0+ +static int cam_cc_sc7180_probe (struct platform_device *pdev) +{ +struct regmap *regmap; +int ret; + +pm_runtime_enable (&pdev->dev); + ret =pm_clk_create (&pdev->dev); +if (ret) +return ret; + + ret =pm_clk_add (&pdev->dev,"xo" ); +if (ret <0 ) { +dev_err (&pdev->dev,"Failed to acquire XO clock\n" ); + goto disable_pm_runtime; + } + + ret =pm_clk_add (&pdev->dev,"iface" ); +if (ret <0 ) { +dev_err (&pdev->dev,"Failed to acquire iface clock\n" ); + goto disable_pm_runtime; + } + + ret =pm_clk_runtime_resume (&pdev->dev); +if (ret) { +dev_err (&pdev->dev,"pm runtime resume failed\n" ); + goto destroy_pm_clk; + } + + regmap =qcom_cc_map (pdev, &cam_cc_sc7180_desc); +if (IS_ERR (regmap)) { + ret =PTR_ERR (regmap); + goto destroy_pm_clk; + }drivers/clk/qcom/camcc-sc7180.c line 1692
Quoted 10 lines
drivers/clk/qcom/camcc-sc7180.c new file +10
-0+ +clk_fabia_pll_configure (&cam_cc_pll0, regmap, &cam_cc_pll0_config); +clk_fabia_pll_configure (&cam_cc_pll1, regmap, &cam_cc_pll1_config); +clk_agera_pll_configure (&cam_cc_pll2, regmap, &cam_cc_pll2_config); +clk_fabia_pll_configure (&cam_cc_pll3, regmap, &cam_cc_pll3_config); + + ret =qcom_cc_really_probe (pdev, &cam_cc_sc7180_desc, regmap); +if (ret) { +dev_err (&pdev->dev,"Failed to register CAM CC clocks\n" ); + goto suspend_pm_runtime;ret is non-zero here
drivers/clk/qcom/camcc-sc7180.c line 1696
Quoted 4 lines
drivers/clk/qcom/camcc-sc7180.c new file +4
-0+ } + +suspend_pm_runtime: + ret =pm_clk_runtime_suspend (&pdev->dev);But then it is overwritten here.
Quoted 7 lines
drivers/clk/qcom/camcc-sc7180.c line 1700
Quoted 4 lines
drivers/clk/qcom/camcc-sc7180.c new file +4
-0+if (ret) +dev_err (&pdev->dev,"pm runtime suspend failed\n" ); + +return 0 ;And we return 0 when there was a failure to probe the clks?
I will clean the error path in the next patch.
Quoted 9 lines
Quoted 9 lines
drivers/clk/qcom/camcc-sc7180.c new file +9
-0+ +destroy_pm_clk: +pm_clk_destroy (&pdev->dev); + +disable_pm_runtime: +pm_runtime_disable (&pdev->dev); + +return ret; +}
Signature · 4 lines
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