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FAILED: patch "[PATCH] drm/amd/pm: fix pcie information for sienna cichlid" failed to apply to 5.9-stable tree

PATCH [email protected] 1 participant 1 message Nov 3, 2020

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Stable branch DRM drivers Radeon and amdgpu DRM drivers AMD powerplay and SWSMU
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The patch below does not apply to the 5.9-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 9a2f408f5406df567a3515f4cb5c2ce1bde64501 Mon Sep 17 00:00:00 2001
From: Likun Gao <[email protected]>
Date: Tue, 20 Oct 2020 16:29:30 +0800
Subject: [PATCH] drm/amd/pm: fix pcie information for sienna cichlid

Fix the function used for sienna cichlid to get correct PCIE information by pp_dpm_pcie.

Signed-off-by Likun Gao <[email protected]>
Reviewed-by Hawking Zhang <[email protected]>
Reviewed-by Kenneth Feng <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
Cc [email protected] # 5.9.x
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +2 -2
index ca2abb2e5340..d708b383f83b 100644
@@ -962,8 +962,8 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
 		}
 		break;
 	case SMU_PCIE:
-		gen_speed = smu_v11_0_get_current_pcie_link_speed(smu);
-		lane_width = smu_v11_0_get_current_pcie_link_width(smu);
+		gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
+		lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 		for (i = 0; i < NUM_LINK_LEVELS; i++)
 			size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 					(dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :