patch "iio: adc: stm32-adc: fix a regression when using dma and irq" added to staging-linus
Subsystems (3)
This is a note to let you know that I've just added the patch titled
iio: adc: stm32-adc: fix a regression when using dma and irq
to my staging git tree which can be found at
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git
in the staging-linus branch.
The patch will show up in the next release of the linux-next tree (usually sometime within the next 24 hours during the week.)
The patch will hopefully also be merged in Linus's tree for the next -rc kernel release.
If you have any questions about this process, please let me know.
From 695e2f5c289bb7f8b85351dcfa35fa236e0200a4 Mon Sep 17 00:00:00 2001
From: Olivier Moysan <[email protected]>
Date: Wed, 21 Oct 2020 10:53:13 +0200
Subject: iio: adc: stm32-adc: fix a regression when using dma and irq
Since overrun interrupt support has been added, there's a regression when two ADCs are used at the same time, with:
- an ADC configured to use IRQs. EOCIE bit is set. The handler is normally called in this case.
- an ADC configured to use DMA. EOCIE bit isn't set. EOC triggers the DMA request. It's then automatically cleared by DMA read. But the handler gets called due to status bit is temporarily set (IRQ triggered by the other ADC).
This is a regression as similar issue had been fixed earlier by commit dcb10920179a ("iio: adc: stm32-adc:
fix a race when using several adcs with dma and irq"). Issue is that stm32_adc_eoc_enabled() returns non-zero value (always) since OVR bit has been added and enabled for both DMA and IRQ case.
Remove OVR mask in IER register, and rely only on CSR status for overrun. To avoid subsequent calls to interrupt routine on overrun, CSR OVR bit has to be cleared. CSR OVR bit cannot be cleared directly by software. To do this ADC must be stopped first, and OVR bit in ADC ISR has to be cleared.
Also add a check in ADC IRQ handler to report spurious IRQs.
--- drivers/iio/adc/stm32-adc-core.c | 41 +++++++++++--------------- drivers/iio/adc/stm32-adc.c | 50 ++++++++++++++++++++++++++++++-- 2 files changed, 65 insertions(+), 26 deletions(-)
drivers/iio/adc/stm32-adc-core.c +17 -24
@@ -41,18 +41,16 @@* struct stm32_adc_common_regs - stm32 common registers * @csr: common status register offset * @ccr: common control register offset -* @eoc1_msk: adc1 end of conversion flag in @csr -* @eoc2_msk: adc2 end of conversion flag in @csr -* @eoc3_msk: adc3 end of conversion flag in @csr +* @eoc_msk: array of eoc (end of conversion flag) masks in csr for adc1..n +* @ovr_msk: array of ovr (overrun flag) masks in csr for adc1..n * @ier: interrupt enable register offset for each adc * @eocie_msk: end of conversion interrupt enable mask in @ier */ struct stm32_adc_common_regs {u32 csr;u32 ccr; -u32 eoc1_msk; -u32 eoc2_msk; -u32 eoc3_msk; +u32 eoc_msk[STM32_ADC_MAX_ADCS ]; +u32 ovr_msk[STM32_ADC_MAX_ADCS ];u32 ier;u32 eocie_msk; };
@@ -282,21 +280,20 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { .csr =STM32F4_ADC_CSR , .ccr =STM32F4_ADC_CCR , - .eoc1_msk =STM32F4_EOC1 |STM32F4_OVR1 , - .eoc2_msk =STM32F4_EOC2 |STM32F4_OVR2 , - .eoc3_msk =STM32F4_EOC3 |STM32F4_OVR3 , + .eoc_msk = {STM32F4_EOC1 ,STM32F4_EOC2 ,STM32F4_EOC3 }, + .ovr_msk = {STM32F4_OVR1 ,STM32F4_OVR2 ,STM32F4_OVR3 }, .ier =STM32F4_ADC_CR1 , - .eocie_msk =STM32F4_EOCIE |STM32F4_OVRIE , + .eocie_msk =STM32F4_EOCIE , };/* STM32H7 common registers definitions */ static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { .csr =STM32H7_ADC_CSR , .ccr =STM32H7_ADC_CCR , - .eoc1_msk =STM32H7_EOC_MST |STM32H7_OVR_MST , - .eoc2_msk =STM32H7_EOC_SLV |STM32H7_OVR_SLV , + .eoc_msk = {STM32H7_EOC_MST ,STM32H7_EOC_SLV }, + .ovr_msk = {STM32H7_OVR_MST ,STM32H7_OVR_SLV }, .ier =STM32H7_ADC_IER , - .eocie_msk =STM32H7_EOCIE |STM32H7_OVRIE , + .eocie_msk =STM32H7_EOCIE , };static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS ] = {
@@ -318,6 +315,7 @@ static void stm32_adc_irq_handler(struct irq_desc *desc) {struct stm32_adc_priv *priv =irq_desc_get_handler_data (desc);struct irq_chip *chip =irq_desc_get_chip (desc); +int i;u32 status;chained_irq_enter (chip, desc);
@@ -335,17 +333,12 @@ static void stm32_adc_irq_handler(struct irq_desc *desc)* before invoking the interrupt handler (e.g. call ISR only for * IRQ-enabled ADCs). */ -if (status & priv->cfg->regs->eoc1_msk && -stm32_adc_eoc_enabled (priv,0 )) -generic_handle_irq (irq_find_mapping (priv->domain,0 )); - -if (status & priv->cfg->regs->eoc2_msk && -stm32_adc_eoc_enabled (priv,1 )) -generic_handle_irq (irq_find_mapping (priv->domain,1 )); - -if (status & priv->cfg->regs->eoc3_msk && -stm32_adc_eoc_enabled (priv,2 )) -generic_handle_irq (irq_find_mapping (priv->domain,2 )); +for (i =0 ; i < priv->cfg->num_irqs; i++) { +if ((status & priv->cfg->regs->eoc_msk[i] && +stm32_adc_eoc_enabled (priv, i)) || + (status & priv->cfg->regs->ovr_msk[i])) +generic_handle_irq (irq_find_mapping (priv->domain, i)); + }chained_irq_exit (chip, desc); };
drivers/iio/adc/stm32-adc.c +48 -2
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