FAILED: patch "[PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR" failed to apply to 5.11-stable tree

PATCH In review [email protected] 2 participants 3 messages Feb 28, 2021 – Mar 1, 2021

Subsystems (3)

Stable branch Arm/CoreSight framework and drivers Hardware tracing facilities

lore

Share & tools

lore

[email protected]

author maintainer

2021-02-28 13:52 UTC #0 lore raw

The patch below does not apply to the 5.11-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From f72896063396b0cb205cbf0fd76ec6ab3ca11c8a Mon Sep 17 00:00:00 2001
From: Suzuki K Poulose <[email protected]>
Date: Mon, 1 Feb 2021 11:13:51 -0700
Subject: [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR

TRCSTALLCTLR register is only implemented if

TRCIDR3.STALLCTL == 0b1

Make sure the driver touches the register only it is implemented.

Link https://lore.kernel.org/r/[email protected] open here

Cc [email protected]

Cc Mathieu Poirier <[email protected]>

Cc Mike Leach <[email protected]>

Cc Leo Yan <[email protected]>

Signed-off-by Suzuki K Poulose <[email protected]>

Signed-off-by Mathieu Poirier <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

Signed-off-by Greg Kroah-Hartman <[email protected]>

drivers/hwtracing/coresight/coresight-etm4x-core.c +6 -3

index 473ab7480a36..5017d33ba4f5 100644
@@ -306,7 +306,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 	etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
 	etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
 	etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
-	etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
+	if (drvdata->stallctl)
+		etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
 	etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
 	etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
 	etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);

@@ -1463,7 +1464,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 	state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
 	state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
 	state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
-	state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
+	if (drvdata->stallctl)
+		state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
 	state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
 	state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
 	state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);

@@ -1575,7 +1577,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 	etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
 	etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
 	etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
-	etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
+	if (drvdata->stallctl)
+		etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
 	etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
 	etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
 	etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);

drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +1 -1

index b646d53a3133..0995a10790f4 100644
@@ -389,7 +389,7 @@ static ssize_t mode_store(struct device *dev,
 		config->eventctrl1 &= ~BIT(12);
 
 	/* bit[8], Instruction stall bit */
-	if (config->mode & ETM_MODE_ISTALL_EN)
+	if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true))
 		config->stall_ctrl |= BIT(8);
 	else
 		config->stall_ctrl &= ~BIT(8);

Suzuki K Poulose

maintainer

2021-03-01 12:16 UTC #1 lore raw

PATCH 1/1 coresight: etm4x: Handle accesses to TRCSTALLCTLR

commit f72896063396b0cb205cbf0fd76ec6ab3ca11c8a upstream

TRCSTALLCTLR register is only implemented if

TRCIDR3.STALLCTL == 0b1

Make sure the driver touches the register only it is implemented.

Link https://lore.kernel.org/r/[email protected] open here

Cc [email protected] # v5.11-

Cc Mathieu Poirier <[email protected]>

Cc Mike Leach <[email protected]>

Cc Leo Yan <[email protected]>

Signed-off-by Suzuki K Poulose <[email protected]>

---
 drivers/hwtracing/coresight/coresight-etm4x-core.c  | 9 ++++++---
 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

drivers/hwtracing/coresight/coresight-etm4x-core.c +6 -3

index b20b6ff17cf6..8ff35b9397da 100644
@@ -226,7 +226,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 	writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 	writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 	writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
-	writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
+	if (drvdata->stallctl)
+		writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 	writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
 	writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
 	writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);

@@ -1288,7 +1289,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 	state->trcauxctlr = readl(drvdata->base + TRCAUXCTLR);
 	state->trceventctl0r = readl(drvdata->base + TRCEVENTCTL0R);
 	state->trceventctl1r = readl(drvdata->base + TRCEVENTCTL1R);
-	state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
+	if (drvdata->stallctl)
+		state->trcstallctlr = readl(drvdata->base + TRCSTALLCTLR);
 	state->trctsctlr = readl(drvdata->base + TRCTSCTLR);
 	state->trcsyncpr = readl(drvdata->base + TRCSYNCPR);
 	state->trcccctlr = readl(drvdata->base + TRCCCCTLR);

@@ -1397,7 +1399,8 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 	writel_relaxed(state->trcauxctlr, drvdata->base + TRCAUXCTLR);
 	writel_relaxed(state->trceventctl0r, drvdata->base + TRCEVENTCTL0R);
 	writel_relaxed(state->trceventctl1r, drvdata->base + TRCEVENTCTL1R);
-	writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
+	if (drvdata->stallctl)
+		writel_relaxed(state->trcstallctlr, drvdata->base + TRCSTALLCTLR);
 	writel_relaxed(state->trctsctlr, drvdata->base + TRCTSCTLR);
 	writel_relaxed(state->trcsyncpr, drvdata->base + TRCSYNCPR);
 	writel_relaxed(state->trcccctlr, drvdata->base + TRCCCCTLR);

drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +1 -1

index 989ce7b8ade7..4682f2613996 100644
@@ -389,7 +389,7 @@ static ssize_t mode_store(struct device *dev,
 		config->eventctrl1 &= ~BIT(12);
 
 	/* bit[8], Instruction stall bit */
-	if (config->mode & ETM_MODE_ISTALL_EN)
+	if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl == true))
 		config->stall_ctrl |= BIT(8);
 	else
 		config->stall_ctrl &= ~BIT(8);

Signature · 1 line

2.24.1

Greg KH

author maintainer

2021-03-01 12:23 UTC #2 lore raw

Re: [PATCH] coresight: etm4x: Handle accesses to TRCSTALLCTLR

Quoted 14 lines · Suzuki K Poulose

commit f72896063396b0cb205cbf0fd76ec6ab3ca11c8a upstream
TRCSTALLCTLR register is only implemented if
   TRCIDR3.STALLCTL == 0b1
Make sure the driver touches the register only it is implemented.
Link https://lore.kernel.org/r/[email protected] open here
Cc [email protected] # v5.11-
Cc Mathieu Poirier <[email protected]>
Cc Mike Leach <[email protected]>
Cc Leo Yan <[email protected]>
Signed-off-by Suzuki K Poulose <[email protected]>

Quoted 4 lines

---
 drivers/hwtracing/coresight/coresight-etm4x-core.c  | 9 ++++++---
 drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

Now queued up to 5.10.y and 5.11.y, thanks.

greg k-h