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FAILED: patch "[PATCH] arm64: Extend workaround for erratum 1024718 to all versions" failed to apply to 4.19-stable tree

PATCH [email protected] 1 participant 1 message Mar 1, 2021

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The patch below does not apply to the 4.19-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From c0b15c25d25171db4b70cc0b7dbc1130ee94017d Mon Sep 17 00:00:00 2001
From: Suzuki K Poulose <[email protected]>
Date: Wed, 3 Feb 2021 23:00:57 +0000
Subject: [PATCH] arm64: Extend workaround for erratum 1024718 to all versions
of Cortex-A55

The erratum 1024718 affects Cortex-A55 r0p0 to r2p0. However we apply the work around for r0p0 - r1p0. Unfortunately this won't be fixed for the future revisions for the CPU. Thus extend the work around for all versions of A55, to cover for r2p0 and any future revisions.

Cc Catalin Marinas <[email protected]>
Cc Will Deacon <[email protected]>
Cc James Morse <[email protected]>
Cc Kunihiko Hayashi <[email protected]>
[will: Update Kconfig help text]
arch/arm64/Kconfig +1 -1
index f39568b28ec1..3dfb25afa616 100644
@@ -522,7 +522,7 @@ config ARM64_ERRATUM_1024718
 	help
 	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
 
-	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
+	  Affected Cortex-A55 cores (all revisions) could cause incorrect
 	  update of the hardware dirty bit when the DBM/AP bits are updated
 	  without a break-before-make. The workaround is to disable the usage
 	  of hardware DBM locally on the affected cores. CPUs not affected by
arch/arm64/kernel/cpufeature.c +1 -1
index e99eddec0a46..db400ca77427 100644
@@ -1455,7 +1455,7 @@ static bool cpu_has_broken_dbm(void)
 	/* List of CPUs which have broken DBM support. */
 	static const struct midr_range cpus[] = {
 #ifdef CONFIG_ARM64_ERRATUM_1024718
-		MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
+		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 		/* Kryo4xx Silver (rdpe => r1p0) */
 		MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
 #endif