FAILED: patch "[PATCH] counter: stm32-timer-cnt: fix ceiling miss-alignment with" failed to apply to 5.4-stable tree
Subsystems (4)
[email protected]
maintainerThe patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From b14d72ac731753708a7c1a6b3657b9312b6f0042 Mon Sep 17 00:00:00 2001
From: Fabrice Gasnier <[email protected]>
Date: Wed, 3 Mar 2021 18:49:49 +0100
Subject: [PATCH] counter: stm32-timer-cnt: fix ceiling miss-alignment with
reload register
Ceiling value may be miss-aligned with what's actually configured into the ARR register. This is seen after probe as currently the ARR value is zero, whereas ceiling value is set to the maximum. So:
- reading ceiling reports zero
- in case the counter gets enabled without any prior configuration, it won't count.
- in case the function gets set by the user 1st, (priv->ceiling) is used.
Fix it by getting rid of the cached "priv->ceiling" variable. Rather use the ARR register value directly by using regmap read or write when needed. There should be no drawback on performance as priv->ceiling isn't used in performance critical path.
There's also no point in writing ARR while setting function (sms), so it can be safely removed.
drivers/counter/stm32-timer-cnt.c +3 -8
@@ -31,7 +31,6 @@ struct stm32_timer_cnt {struct counter_device counter;struct regmap *regmap;struct clk *clk; -u32 ceiling;u32 max_arr;bool enabled;struct stm32_timer_regs bak;
@@ -75,8 +74,10 @@ static int stm32_count_write(struct counter_device *counter, const unsigned long val) {struct stm32_timer_cnt *const priv = counter->priv; +u32 ceiling; -if (val > priv->ceiling) +regmap_read (priv->regmap,TIM_ARR , &ceiling); +if (val > ceiling)return -EINVAL ;return regmap_write (priv->regmap,TIM_CNT , val);
@@ -138,10 +139,6 @@ static int stm32_count_function_set(struct counter_device *counter,regmap_update_bits (priv->regmap,TIM_CR1 ,TIM_CR1_CEN ,0 ); -/* TIMx_ARR register shouldn't be buffered (ARPE=0) */ -regmap_update_bits (priv->regmap,TIM_CR1 ,TIM_CR1_ARPE ,0 ); -regmap_write (priv->regmap,TIM_ARR , priv->ceiling); -regmap_update_bits (priv->regmap,TIM_SMCR ,TIM_SMCR_SMS , sms);/* Make sure that registers are updated */
@@ -199,7 +196,6 @@ static ssize_t stm32_count_ceiling_write(struct counter_device *counter,regmap_update_bits (priv->regmap,TIM_CR1 ,TIM_CR1_ARPE ,0 );regmap_write (priv->regmap,TIM_ARR , ceiling); - priv->ceiling = ceiling;return len; }
@@ -374,7 +370,6 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) priv->regmap = ddata->regmap; priv->clk = ddata->clk; - priv->ceiling = ddata->max_arr; priv->max_arr = ddata->max_arr; priv->counter.name =dev_name (dev);
Sudip Mukherjee
Acked-by William Breathitt GrayHi Greg,
Quoted 5 lines · On Mon, Mar 22, 2021 at 10:12:18AM +0100, [email protected] wrote:
The patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
Here is the bakport.
--
Regards
Sudip
From 90f7d51d99c6ebe7e5eb925da018653846eb05bd Mon Sep 17 00:00:00 2001
From: Fabrice Gasnier <[email protected]>
Date: Wed, 3 Mar 2021 18:49:49 +0100
Subject: [PATCH] counter: stm32-timer-cnt: fix ceiling miss-alignment with
reload register
commit b14d72ac731753708a7c1a6b3657b9312b6f0042 upstream
Ceiling value may be miss-aligned with what's actually configured into the ARR register. This is seen after probe as currently the ARR value is zero, whereas ceiling value is set to the maximum. So:
- reading ceiling reports zero
- in case the counter gets enabled without any prior configuration, it won't count.
- in case the function gets set by the user 1st, (priv->ceiling) is used.
Fix it by getting rid of the cached "priv->ceiling" variable. Rather use the ARR register value directly by using regmap read or write when needed. There should be no drawback on performance as priv->ceiling isn't used in performance critical path.
There's also no point in writing ARR while setting function (sms), so it can be safely removed.
--- drivers/counter/stm32-timer-cnt.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-)
drivers/counter/stm32-timer-cnt.c +3 -9
@@ -24,7 +24,6 @@ struct stm32_timer_cnt {struct counter_device counter;struct regmap *regmap;struct clk *clk; -u32 ceiling;u32 max_arr; };
@@ -67,14 +66,15 @@ static int stm32_count_write(struct counter_device *counter, struct counter_count_write_value *val) {struct stm32_timer_cnt *const priv = counter->priv; -u32 cnt; +u32 cnt, ceiling;int err; err =counter_count_write_value_get (&cnt,COUNTER_COUNT_POSITION , val);if (err)return err; -if (cnt > priv->ceiling) +regmap_read (priv->regmap,TIM_ARR , &ceiling); +if (cnt > ceiling)return -EINVAL ;return regmap_write (priv->regmap,TIM_CNT , cnt);
@@ -136,10 +136,6 @@ static int stm32_count_function_set(struct counter_device *counter,regmap_update_bits (priv->regmap,TIM_CR1 ,TIM_CR1_CEN ,0 ); -/* TIMx_ARR register shouldn't be buffered (ARPE=0) */ -regmap_update_bits (priv->regmap,TIM_CR1 ,TIM_CR1_ARPE ,0 ); -regmap_write (priv->regmap,TIM_ARR , priv->ceiling); -regmap_update_bits (priv->regmap,TIM_SMCR ,TIM_SMCR_SMS , sms);/* Make sure that registers are updated */
@@ -197,7 +193,6 @@ static ssize_t stm32_count_ceiling_write(struct counter_device *counter,regmap_update_bits (priv->regmap,TIM_CR1 ,TIM_CR1_ARPE ,0 );regmap_write (priv->regmap,TIM_ARR , ceiling); - priv->ceiling = ceiling;return len; }
@@ -369,7 +364,6 @@ static int stm32_timer_cnt_probe(struct platform_device *pdev) priv->regmap = ddata->regmap; priv->clk = ddata->clk; - priv->ceiling = ddata->max_arr; priv->max_arr = ddata->max_arr; priv->counter.name =dev_name (dev);
Signature · 1 line
2.30.2
Greg KH
maintainerQuoted 10 lines · Sudip Mukherjee
Hi Greg,
Quoted 5 lines · On Mon, Mar 22, 2021 at 10:12:18AM +0100, [email protected] wrote:
The patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.Here is the bakport.
Now queued up, thanks.
greg k-h