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ARM: dts: rockchip: set correct dwc2 params for cortex-a9 socs

PATCH New Heiko Stübner 1 participant 4 messages Aug 2, 2015 – Aug 8, 2015

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Heiko Stübner

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#0 lore raw

PATCH 1/3 ARM: dts: rockchip: set correct dwc2 params for cortex-a9 socs

According to the manual, the fifo sizes are the same as on later socs like the rk3288 and this also fixes an error about "insufficient fifo memory", as it seems the values read from the ip are wrong.

Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/boot/dts/rk3xxx.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm/boot/dts/rk3xxx.dtsi +6 -0
index a2ae9f3..c571ac8 100644
@@ -172,6 +172,11 @@
 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_OTG0>;
 		clock-names = "otg";
+		dr_mode = "otg";
+		g-np-tx-fifo-size = <16>;
+		g-rx-fifo-size = <275>;
+		g-tx-fifo-size = <256 128 128 64 64 32>;
+		g-use-dma;
 		status = "disabled";
 	};
 

@@ -181,6 +186,7 @@
 		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru HCLK_OTG1>;
 		clock-names = "otg";
+		dr_mode = "host";
 		status = "disabled";
 	};
Signature · 1 line
2.1.4
author maintainer Applied
#1 lore raw

PATCH 1/3 ARM: dts: rockchip: set correct dwc2 params for cortex-a9 socs

Am Sonntag, 2. August 2015, 23:43:12 schrieb Heiko St?bner:

Quoted 6 lines

According to the manual, the fifo sizes are the same as on later socs like the rk3288 and this also fixes an error about "insufficient fifo memory", as it seems the values read from the ip are wrong.

Signed-off-by Heiko Stuebner <[email protected]>

---

applied all 3 patches to my dts branch

author maintainer
#2 lore raw

PATCH 2/3 ARM: dts: rockchip: add usb phys to Cortex-A9 socs

In reply to Heiko Stübner

This adds the usbphy nodes to rk3066 and rk3188, which share the usb hosts in rk3xxx.dtsi and also enables it on boards based around these socs.

The usb-phy itself is the same as used on the rk3288 already.

Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/boot/dts/rk3066a-marsboard.dts |  4 ++++
 arch/arm/boot/dts/rk3066a-rayeager.dts  |  4 ++++
 arch/arm/boot/dts/rk3066a.dtsi          | 22 ++++++++++++++++++++++
 arch/arm/boot/dts/rk3188-radxarock.dts  |  4 ++++
 arch/arm/boot/dts/rk3188.dtsi           | 22 ++++++++++++++++++++++
 arch/arm/boot/dts/rk3xxx.dtsi           |  4 ++++
 6 files changed, 60 insertions(+)
arch/arm/boot/dts/rk3066a-marsboard.dts +4 -0
index 4355966..08f5b43 100644
@@ -202,6 +202,10 @@
 	status = "okay";
 };
 
+&usbphy {
+	status = "okay";
+};
+
 &wdt {
 	status = "okay";
 };
arch/arm/boot/dts/rk3066a-rayeager.dts +4 -0
index 7ccd376..e36383c 100644
@@ -460,6 +460,10 @@
 	status = "okay";
 };
 
+&usbphy {
+	status = "okay";
+};
+
 &usb_otg {
 	status = "okay";
 };
arch/arm/boot/dts/rk3066a.dtsi +22 -0
index d32229b..870e6f5 100644
@@ -169,6 +169,28 @@
 		clock-names = "timer", "pclk";
 	};
 
+	usbphy: phy {
+		compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		usbphy0: usb-phy0 {
+			#phy-cells = <0>;
+			reg = <0x17c>;
+			clocks = <&cru SCLK_OTGPHY0>;
+			clock-names = "phyclk";
+		};
+
+		usbphy1: usb-phy1 {
+			#phy-cells = <0>;
+			reg = <0x188>;
+			clocks = <&cru SCLK_OTGPHY1>;
+			clock-names = "phyclk";
+		};
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3066a-pinctrl";
 		rockchip,grf = <&grf>;
arch/arm/boot/dts/rk3188-radxarock.dts +4 -0
index 4bb014d..d2180e5 100644
@@ -359,6 +359,10 @@
 	status = "okay";
 };
 
+&usbphy {
+	status = "okay";
+};
+
 &usb_host {
 	status = "okay";
 };
arch/arm/boot/dts/rk3188.dtsi +22 -0
index 0f23aed..3163042 100644
@@ -130,6 +130,28 @@
 		#reset-cells = <1>;
 	};
 
+	usbphy: phy {
+		compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
+		rockchip,grf = <&grf>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		usbphy0: usb-phy0 {
+			#phy-cells = <0>;
+			reg = <0x10c>;
+			clocks = <&cru SCLK_OTGPHY0>;
+			clock-names = "phyclk";
+		};
+
+		usbphy1: usb-phy1 {
+			#phy-cells = <0>;
+			reg = <0x11c>;
+			clocks = <&cru SCLK_OTGPHY1>;
+			clock-names = "phyclk";
+		};
+	};
+
 	pinctrl: pinctrl {
 		compatible = "rockchip,rk3188-pinctrl";
 		rockchip,grf = <&grf>;
arch/arm/boot/dts/rk3xxx.dtsi +4 -0
index c571ac8..4497d28 100644
@@ -177,6 +177,8 @@
 		g-rx-fifo-size = <275>;
 		g-tx-fifo-size = <256 128 128 64 64 32>;
 		g-use-dma;
+		phys = <&usbphy0>;
+		phy-names = "usb2-phy";
 		status = "disabled";
 	};
 

@@ -187,6 +189,8 @@
 		clocks = <&cru HCLK_OTG1>;
 		clock-names = "otg";
 		dr_mode = "host";
+		phys = <&usbphy1>;
+		phy-names = "usb2-phy";
 		status = "disabled";
 	};
Signature · 1 line
2.1.4
author maintainer
#3 lore raw

PATCH 3/3 ARM: dts: rockchip: enable usb controller on marsboard

In reply to Heiko Stübner

This enables the previously disabled usb controllers on the marsboard and makes it possible to for example mount usb mass storage devices.

Signed-off-by Heiko Stuebner <[email protected]>
---
 arch/arm/boot/dts/rk3066a-marsboard.dts | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/boot/dts/rk3066a-marsboard.dts +8 -0
index 08f5b43..bae965c 100644
@@ -206,6 +206,14 @@
 	status = "okay";
 };
 
+&usb_host {
+	status = "okay";
+};
+
+&usb_otg {
+	status = "okay";
+};
+
 &wdt {
 	status = "okay";
 };
Signature · 1 line
2.1.4