FAILED: patch "[PATCH] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again" failed to apply to 5.4-stable tree
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[email protected]
maintainerThe patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 04d019961fd15de92874575536310243a0d4c5c5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <[email protected]>
Date: Wed, 21 Apr 2021 18:33:59 +0300
Subject: [PATCH] drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
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We've defined C0DRB3/C1DRB3 as 16 bit registers, so access them as such.
Fixes 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences")
Reviewed-by Chris Wilson <[email protected]>
Signed-off-by Ville Syrjälä <[email protected]>
(cherry picked from commit f765a5b48c667bdada5e49d5e0f23f8c0687b21b)
Signed-off-by Jani Nikula <[email protected]>
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +2 -2
@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)* banks of memory are paired and unswizzled on the * uneven portion, so leave that as unknown. */ -if (intel_uncore_read (uncore,C0DRB3 ) == -intel_uncore_read (uncore,C1DRB3 )) { +if (intel_uncore_read16 (uncore,C0DRB3 ) == +intel_uncore_read16 (uncore,C1DRB3 )) { swizzle_x =I915_BIT_6_SWIZZLE_9_10 ; swizzle_y =I915_BIT_6_SWIZZLE_9 ; }