riscv: Add DMA_COHERENT support for Allwinner D1

arch/riscv/include/asm/tlbflush.h +9 -0

+static inline void local_flush_tlb_all_asid(unsigned long asid)
+{
+	__asm__ __volatile__ ("sfence.vma x0, %0"
+			:
+			: "r" (asid)
+			: "memory");
+}
+
+static inline void local_flush_tlb_range_asid(unsigned long start,

arch/riscv/mm/tlbflush.c +16 -0

+static void __sbi_tlb_flush_range_asid(struct cpumask *cmask,
+				       unsigned long start,
+				       unsigned long size,
+				       unsigned long asid)
+{
+	struct cpumask hmask;
+	unsigned int cpuid;
+
+	if (cpumask_empty(cmask))
+		return;
+
+	cpuid = get_cpu();
+
+	if (cpumask_any_but(cmask, cpuid) >= nr_cpu_ids) {
+		if (size == -1)
+			local_flush_tlb_all_asid(asid);

arch/riscv/mm/tlbflush.c +11 -2

+
 void flush_tlb_mm(struct mm_struct *mm)
 {
-	__sbi_tlb_flush_range(mm_cpumask(mm), 0, -1);
+	if (static_branch_unlikely(&use_asid_allocator))
+		__sbi_tlb_flush_range_asid(mm_cpumask(mm), 0, -1,
+					   atomic_long_read(&mm->context.id));
+	else
+		__sbi_tlb_flush_range(mm_cpumask(mm), 0, -1);
 }
 
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
 {
-	__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE);
+	if (static_branch_unlikely(&use_asid_allocator))
+		__sbi_tlb_flush_range_asid(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE,
+					   atomic_long_read(&vma->vm_mm->context.id));
+	else
+		__sbi_tlb_flush_range(mm_cpumask(vma->vm_mm), addr, PAGE_SIZE);
 }

NAK, no SOC must ever mess with pagetable attributes.

From: Guo Ren <[email protected]>

The dma-noncoherent SOCs need different virtual memory mappings with different attributes:
- noncached + Strong Order (for IO/DMA descriptor)
- noncached + Weak Order (for writecombine usage, eg: frame buffer)

All above base on PTE attributes by MMU hardware. That means address attributes are determined by PTE entry, not PMA. RISC-V soc vendors have defined their own custom PTE attributes for dma-noncoherency.

This patch violates the Privilege Spec section 4.4.1 that clearly states:

"Bits63–54 are reserved for future standard use and must be zeroed by software for forward compatibility"

Standard use means that valid values can only be defined by the Priv. Spec, not by the vendor (otherwise they'd be marked as "custom use" or "platform use"), and since they "must" be zeroed by software we 'll be violating the Privilege Spec if we do otherwise.

From: Guo Ren <[email protected]>

To support DMA device in a non-coherent interconnect SOC system, we need the below facilities:
- Changing a virtual memory mapping region attributes from cacheable to noncache + strong order which used in DMA descriptors.
- Add noncache + weakorder virtual memory attributes for dma mapping.
- Syncing the cache with memory before DMA start and after DMA end with vendor custom CMO instructions.

This patch enables linux kernel generic dma-noncoherency infrastructure and introduces new sbi_ecall API for dma_sync.

arch/riscv/include/asm/sbi.h +1 -0

@@ -27,6 +27,7 @@ enum sbi_ext_id {
+       SBI_EXT_DMA = 0xAB150401,
 

Signed-off-by Guo Ren <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Anup Patel <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Maxime Ripard <[email protected]>

---
 arch/riscv/Kconfig               |  5 ++++
 arch/riscv/include/asm/pgtable.h | 26 ++++++++++++++++++++
 arch/riscv/include/asm/sbi.h     | 15 ++++++++++++
 arch/riscv/kernel/sbi.c          | 19 ++++++++++++++
 arch/riscv/mm/Makefile           |  1 +
 arch/riscv/mm/dma-mapping.c      | 53 ++++++++++++++++++++++++++++++++++++++++
 6 files changed, 119 insertions(+)
 create mode 100644 arch/riscv/mm/dma-mapping.c

arch/riscv/Kconfig +5 -0

index 05c4976..817a9bb 100644
@@ -20,6 +20,10 @@ config RISCV
 	select ARCH_HAS_DEBUG_VM_PGTABLE
 	select ARCH_HAS_DEBUG_VIRTUAL if MMU
 	select ARCH_HAS_DEBUG_WX
+	select ARCH_HAS_DMA_PREP_COHERENT
+	select ARCH_HAS_SYNC_DMA_FOR_CPU
+	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
+	select ARCH_HAS_DMA_WRITE_COMBINE
 	select ARCH_HAS_FORTIFY_SOURCE
 	select ARCH_HAS_GCOV_PROFILE_ALL
 	select ARCH_HAS_GIGANTIC_PAGE

@@ -43,6 +47,7 @@ config RISCV
 	select CLONE_BACKWARDS
 	select CLINT_TIMER if !MMU
 	select COMMON_CLK
+	select DMA_DIRECT_REMAP
 	select EDAC_SUPPORT
 	select GENERIC_ARCH_TOPOLOGY if SMP
 	select GENERIC_ATOMIC64 if !64BIT

arch/riscv/include/asm/pgtable.h +26 -0

index 6ddeb49..e1a82b6 100644
@@ -462,6 +462,32 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 	return ptep_test_and_clear_young(vma, address, ptep);
 }
 
+#define pgprot_noncached pgprot_noncached
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+	unsigned long prot = pgprot_val(_prot);
+
+	prot &= ~_PAGE_DMA_MASK;
+	prot |= _PAGE_DMA_IO;
+
+	return __pgprot(prot);
+}
+
+#define pgprot_writecombine pgprot_writecombine
+static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
+{
+	unsigned long prot = pgprot_val(_prot);
+
+	prot &= ~_PAGE_DMA_MASK;
+	prot |= _PAGE_DMA_WC;
+
+	return __pgprot(prot);
+}
+
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+				     unsigned long size, pgprot_t vma_prot);
+
 /*
  * Encode and decode a swap entry
  *

arch/riscv/include/asm/sbi.h +15 -0

index 0d42693..133e88a 100644
@@ -27,6 +27,7 @@ enum sbi_ext_id {
 	SBI_EXT_IPI = 0x735049,
 	SBI_EXT_RFENCE = 0x52464E43,
 	SBI_EXT_HSM = 0x48534D,
+	SBI_EXT_DMA = 0xAB150401,
 };
 
 enum sbi_ext_base_fid {

@@ -63,6 +64,17 @@ enum sbi_ext_hsm_fid {
 	SBI_EXT_HSM_HART_STATUS,
 };
 
+enum sbi_ext_dma_fid {
+	SBI_DMA_SYNC = 0,
+};
+
+enum sbi_dma_sync_data_direction {
+	SBI_DMA_BIDIRECTIONAL = 0,
+	SBI_DMA_TO_DEVICE = 1,
+	SBI_DMA_FROM_DEVICE = 2,
+	SBI_DMA_NONE = 3,
+};
+
 enum sbi_hsm_hart_status {
 	SBI_HSM_HART_STATUS_STARTED = 0,
 	SBI_HSM_HART_STATUS_STOPPED,

@@ -128,6 +140,9 @@ int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
 				unsigned long size,
 				unsigned long asid);
 int sbi_probe_extension(int ext);
+void sbi_dma_sync(unsigned long start,
+		  unsigned long size,
+		  enum sbi_dma_sync_data_direction dir);
 
 /* Check if current SBI specification version is 0.1 or not */
 static inline int sbi_spec_is_0_1(void)

arch/riscv/kernel/sbi.c +4 -0

index 7402a41..c936019 100644
@@ -521,6 +521,25 @@ int sbi_probe_extension(int extid)
 }
 EXPORT_SYMBOL(sbi_probe_extension);
 
+void sbi_dma_sync(unsigned long start,
+		  unsigned long size,
+		  enum sbi_dma_sync_data_direction dir)
+{

arch/riscv/kernel/sbi.c +5 -0

+	__asm__ __volatile__(".long 0x01b0000b");
+#endif
+}
+EXPORT_SYMBOL(sbi_dma_sync);
+
 static long __sbi_base_ecall(int fid)
 {
 	struct sbiret ret;

arch/riscv/mm/Makefile +1 -0

index 7ebaef1..ca0ff90 100644
@@ -13,6 +13,7 @@ obj-y += extable.o
 obj-$(CONFIG_MMU) += fault.o pageattr.o
 obj-y += cacheflush.o
 obj-y += context.o
+obj-y += dma-mapping.o
 
 ifeq ($(CONFIG_MMU),y)
 obj-$(CONFIG_SMP) += tlbflush.o

arch/riscv/mm/dma-mapping.c new file +53 -0

new file mode 100644
index 00000000..4afd9dc
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/dma-map-ops.h>
+#include <asm/sbi.h>
+
+void arch_dma_prep_coherent(struct page *page, size_t size)
+{
+	void *ptr = page_address(page);
+
+	memset(ptr, 0, size);
+	sbi_dma_sync(page_to_phys(page), size, SBI_DMA_BIDIRECTIONAL);
+}
+
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
+		enum dma_data_direction dir)
+{
+	switch (dir) {
+	case DMA_TO_DEVICE:
+	case DMA_FROM_DEVICE:
+	case DMA_BIDIRECTIONAL:
+		sbi_dma_sync(paddr, size, dir);
+		break;
+	default:
+		BUG();
+	}
+}
+
+void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
+		enum dma_data_direction dir)
+{
+	switch (dir) {
+	case DMA_TO_DEVICE:
+		return;
+	case DMA_FROM_DEVICE:
+	case DMA_BIDIRECTIONAL:
+		sbi_dma_sync(paddr, size, dir);
+		break;
+	default:
+		BUG();
+	}
+}
+
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+			      unsigned long size, pgprot_t vma_prot)
+{
+	if (!pfn_valid(pfn))
+		return pgprot_noncached(vma_prot);
+	else if (file->f_flags & O_SYNC)
+		return pgprot_writecombine(vma_prot);
+
+	return vma_prot;
+}
+EXPORT_SYMBOL(phys_mem_access_prot);

Quoted 151 lines · On 2021/6/6 17:04, [email protected] wrote:

From: Guo Ren <[email protected]>

To support DMA device in a non-coherent interconnect SOC system, we need the below facilities:
- Changing a virtual memory mapping region attributes from cacheable to noncache + strong order which used in DMA descriptors.
- Add noncache + weakorder virtual memory attributes for dma mapping.
- Syncing the cache with memory before DMA start and after DMA end with vendor custom CMO instructions.

This patch enables linux kernel generic dma-noncoherency infrastructure and introduces new sbi_ecall API for dma_sync.

arch/riscv/include/asm/sbi.h +1 -0

@@ -27,6 +27,7 @@ enum sbi_ext_id {
+       SBI_EXT_DMA = 0xAB150401,
 

Signed-off-by Guo Ren <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Anup Patel <[email protected]>

Cc Arnd Bergmann <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Maxime Ripard <[email protected]>

---
 arch/riscv/Kconfig               |  5 ++++
 arch/riscv/include/asm/pgtable.h | 26 ++++++++++++++++++++
 arch/riscv/include/asm/sbi.h     | 15 ++++++++++++
 arch/riscv/kernel/sbi.c          | 19 ++++++++++++++
 arch/riscv/mm/Makefile           |  1 +
 arch/riscv/mm/dma-mapping.c      | 53 ++++++++++++++++++++++++++++++++++++++++
 6 files changed, 119 insertions(+)
 create mode 100644 arch/riscv/mm/dma-mapping.c

arch/riscv/Kconfig +5 -0

index 05c4976..817a9bb 100644
@@ -20,6 +20,10 @@ config RISCV
      select ARCH_HAS_DEBUG_VM_PGTABLE
      select ARCH_HAS_DEBUG_VIRTUAL if MMU
      select ARCH_HAS_DEBUG_WX
+     select ARCH_HAS_DMA_PREP_COHERENT
+     select ARCH_HAS_SYNC_DMA_FOR_CPU
+     select ARCH_HAS_SYNC_DMA_FOR_DEVICE
+     select ARCH_HAS_DMA_WRITE_COMBINE
      select ARCH_HAS_FORTIFY_SOURCE
      select ARCH_HAS_GCOV_PROFILE_ALL
      select ARCH_HAS_GIGANTIC_PAGE

@@ -43,6 +47,7 @@ config RISCV
      select CLONE_BACKWARDS
      select CLINT_TIMER if !MMU
      select COMMON_CLK
+     select DMA_DIRECT_REMAP
      select EDAC_SUPPORT
      select GENERIC_ARCH_TOPOLOGY if SMP
      select GENERIC_ATOMIC64 if !64BIT

arch/riscv/include/asm/pgtable.h +26 -0

index 6ddeb49..e1a82b6 100644
@@ -462,6 +462,32 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
      return ptep_test_and_clear_young(vma, address, ptep);
 }
 
+#define pgprot_noncached pgprot_noncached
+static inline pgprot_t pgprot_noncached(pgprot_t _prot)
+{
+     unsigned long prot = pgprot_val(_prot);
+
+     prot &= ~_PAGE_DMA_MASK;
+     prot |= _PAGE_DMA_IO;
+
+     return __pgprot(prot);
+}
+
+#define pgprot_writecombine pgprot_writecombine
+static inline pgprot_t pgprot_writecombine(pgprot_t _prot)
+{
+     unsigned long prot = pgprot_val(_prot);
+
+     prot &= ~_PAGE_DMA_MASK;
+     prot |= _PAGE_DMA_WC;
+
+     return __pgprot(prot);
+}
+
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                  unsigned long size, pgprot_t vma_prot);
+
 /*
  * Encode and decode a swap entry
  *

arch/riscv/include/asm/sbi.h +15 -0

index 0d42693..133e88a 100644
@@ -27,6 +27,7 @@ enum sbi_ext_id {
      SBI_EXT_IPI = 0x735049,
      SBI_EXT_RFENCE = 0x52464E43,
      SBI_EXT_HSM = 0x48534D,
+     SBI_EXT_DMA = 0xAB150401,
 };
 
 enum sbi_ext_base_fid {

@@ -63,6 +64,17 @@ enum sbi_ext_hsm_fid {
      SBI_EXT_HSM_HART_STATUS,
 };
 
+enum sbi_ext_dma_fid {
+     SBI_DMA_SYNC = 0,
+};
+
+enum sbi_dma_sync_data_direction {
+     SBI_DMA_BIDIRECTIONAL = 0,
+     SBI_DMA_TO_DEVICE = 1,
+     SBI_DMA_FROM_DEVICE = 2,
+     SBI_DMA_NONE = 3,
+};
+
 enum sbi_hsm_hart_status {
      SBI_HSM_HART_STATUS_STARTED = 0,
      SBI_HSM_HART_STATUS_STOPPED,

@@ -128,6 +140,9 @@ int sbi_remote_hfence_vvma_asid(const unsigned long *hart_mask,
                              unsigned long size,
                              unsigned long asid);
 int sbi_probe_extension(int ext);
+void sbi_dma_sync(unsigned long start,
+               unsigned long size,
+               enum sbi_dma_sync_data_direction dir);
 
 /* Check if current SBI specification version is 0.1 or not */
 static inline int sbi_spec_is_0_1(void)

arch/riscv/kernel/sbi.c +4 -0

index 7402a41..c936019 100644
@@ -521,6 +521,25 @@ int sbi_probe_extension(int extid)
 }
 EXPORT_SYMBOL(sbi_probe_extension);
 
+void sbi_dma_sync(unsigned long start,
+               unsigned long size,
+               enum sbi_dma_sync_data_direction dir)
+{

arch/riscv/kernel/sbi.c int sbi_probe_extension(int extid) · line 537

Quoted 10 lines

arch/riscv/kernel/sbi.c +10 -0

+#if 0
+     sbi_ecall(SBI_EXT_DMA, SBI_DMA_SYNC, start, size, dir,
+               0, 0, 0);
+#else
+     /* Just for try, it should be in sbi ecall and will be removed before merged */
+     register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1);
+
+     for (; i < ALIGN(start + size, L1_CACHE_BYTES); i += L1_CACHE_BYTES)
+             __asm__ __volatile__(".long 0x02b5000b");
+

Hi, I'm trying to use this patch for my D1 board.

Though the above code will be removed, I notice that the use of the inline assembly is wrong and i (i.e. a0) might not be correctly passed to the assembly code when we are using some other compilers.

It should be __asm__ __volatile__(".long 0x02b5000b" : : "r"(i)).

Thanks,
Wende

Quoted 69 lines

arch/riscv/kernel/sbi.c +5 -0

+     __asm__ __volatile__(".long 0x01b0000b");
+#endif
+}
+EXPORT_SYMBOL(sbi_dma_sync);
+
 static long __sbi_base_ecall(int fid)
 {
      struct sbiret ret;

arch/riscv/mm/Makefile +1 -0

index 7ebaef1..ca0ff90 100644
@@ -13,6 +13,7 @@ obj-y += extable.o
 obj-$(CONFIG_MMU) += fault.o pageattr.o
 obj-y += cacheflush.o
 obj-y += context.o
+obj-y += dma-mapping.o
 
 ifeq ($(CONFIG_MMU),y)
 obj-$(CONFIG_SMP) += tlbflush.o

arch/riscv/mm/dma-mapping.c new file +43 -0

new file mode 100644
index 00000000..4afd9dc
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/dma-map-ops.h>
+#include <asm/sbi.h>
+
+void arch_dma_prep_coherent(struct page *page, size_t size)
+{
+     void *ptr = page_address(page);
+
+     memset(ptr, 0, size);
+     sbi_dma_sync(page_to_phys(page), size, SBI_DMA_BIDIRECTIONAL);
+}
+
+void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
+             enum dma_data_direction dir)
+{
+     switch (dir) {
+     case DMA_TO_DEVICE:
+     case DMA_FROM_DEVICE:
+     case DMA_BIDIRECTIONAL:
+             sbi_dma_sync(paddr, size, dir);
+             break;
+     default:
+             BUG();
+     }
+}
+
+void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
+             enum dma_data_direction dir)
+{
+     switch (dir) {
+     case DMA_TO_DEVICE:
+             return;
+     case DMA_FROM_DEVICE:
+     case DMA_BIDIRECTIONAL:
+             sbi_dma_sync(paddr, size, dir);
+             break;
+     default:
+             BUG();
+     }
+}
+
+pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,

arch/riscv/mm/dma-mapping.c line 53

Quoted 10 lines

arch/riscv/mm/dma-mapping.c new file +10 -0

+                           unsigned long size, pgprot_t vma_prot)
+{
+     if (!pfn_valid(pfn))
+             return pgprot_noncached(vma_prot);
+     else if (file->f_flags & O_SYNC)
+             return pgprot_writecombine(vma_prot);
+
+     return vma_prot;
+}
+EXPORT_SYMBOL(phys_mem_access_prot);

--
Best wishes!
Sincerely,
twd2
https://twd2.me

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +51 -0

+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <2400000>;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcv";
+			mmu-type = "riscv,sv39";
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges;
+
+		reset: reset-sample {
+			compatible = "thead,reset-sample";
+			plic-delegate = <0x0 0x101ffffc>;
+		};
+
+		clint: clint@14000000 {
+			compatible = "riscv,clint0";
+			interrupts-extended = <
+				&cpu0_intc  3 &cpu0_intc  7
+				>;
+			reg = <0x0 0x14000000 0x0 0x04000000>;
+			clint,has-no-64bit-mmio;
+		};
+
+		plic: interrupt-controller@10000000 {
+			#interrupt-cells = <1>;
+			compatible = "riscv,plic0";
+			interrupt-controller;
+			interrupts-extended = <
+				&cpu0_intc  0xffffffff &cpu0_intc  9
+				>;
+			reg = <0x0 0x10000000 0x0 0x04000000>;
+			reg-names = "control";
+			riscv,max-priority = <7>;
+			riscv,ndev = <200>;

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +11 -0

+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x02500000 0x0 0x400>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupt-parent = <&plic>;
+			interrupts = <18>;
+			clocks = <&dummy_apb>;
+			status = "disabled";
+		};
+	};
+};

Hi!

I didn't go through all details. After you fix all comments below, you should run "make dtbs_check" and fix all reported warnings too.

Dne nedelja, 06. junij 2021 ob 11:04:07 CEST je [email protected] napisal(a):

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts

Quoted 52 lines

From: Guo Ren <[email protected]>

Add initial DTS for Allwinner D1 NeZha board having only essential devices (uart, dummy, clock, reset, clint, plic, etc).

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

---
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/allwinner/Makefile             |  2 +
 .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts  | 29 ++++++++
 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi    | 84
++++++++++++++++++++++ 4 files changed, 116 insertions(+)
 create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
 create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts

create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

arch/riscv/boot/dts/Makefile +1 -0

index fe996b8..3e7b264 100644
@@ -2,5 +2,6 @@
 subdir-y += sifive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
 subdir-y += microchip
+subdir-y += allwinner
 
 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/Makefile new file mode 100644 index 00000000..4adbf4b

arch/riscv/boot/dts/allwinner/Makefile new file +2 -0

@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SUNXI) += allwinner-d1-nezha-kit.dtb

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file mode 100644
index 00000000..cd9f7c9

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +0 -0

Board DT names are comprised of soc name and board name, in this case it would be "sun20i-d1-nezha-kit.dts"

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 1

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +1 -0

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

Usually copyrights are added below spdx id.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 9

Quoted 9 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +8 -0

+
+/dts-v1/;
+
+#include "allwinner-d1.dtsi"
+
+/ {
+     #address-cells = <2>;
+     #size-cells = <2>;

This should be part of SoC level DTSI.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 11

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +2 -0

+     model = "Allwinner D1 NeZha Kit";
+     compatible = "allwinner,d1-nezha-kit";

Board specific compatible string should be followed with SoC compatible, in this case "allwinner,sun20i-d1". You should document it too.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 14

Quoted 4 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +3 -0

+
+     chosen {
+             bootargs = "console=ttyS0,115200";

Above line doesn't belong here. If anything, it should be added dynamically by bootloader.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 21

Quoted 8 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +7 -0

+             stdout-path = &serial0;
+     };
+
+     memory@40000000 {
+             device_type = "memory";
+             reg = <0x0 0x40000000 0x0 0x20000000>;
+     };

Ditto for whole memory node.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 24

Quoted 4 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +3 -0

+
+     soc {
+     };

There is no point having empty nodes.

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

Quoted 11 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +5 -0

+};
+
+&serial0 {
+     status = "okay";
+};

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file mode 100644 index 00000000..11cd938

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +0 -0

Current naming approach for Allwinner SoC level DTSI is "sun20i-d1.dtsi".

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi line 7

Quoted 9 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +7 -0

@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 
+
+/dts-v1/;
+
+/ {
+     #address-cells = <2>;
+     #size-cells = <2>;

Since all peripherals and memory are below 4 GiB, why have 64-bit addresses and sizes? It just clutters DT.

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi line 9

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +2 -0

+     model = "Allwinner D1 Soc";
+     compatible = "allwinner,d1-nezha-kit";

Compatible and model don't belong to SoC level DTSI.

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

Quoted 3 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +3 -0

+
+     chosen {
+     };

Remove empty node.

Quoted 57 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +56 -0

+
+     cpus {
+             #address-cells = <1>;
+             #size-cells = <0>;
+             timebase-frequency = <2400000>;
+             cpu@0 {
+                     device_type = "cpu";
+                     reg = <0>;
+                     status = "okay";
+                     compatible = "riscv";
+                     riscv,isa = "rv64imafdcv";
+                     mmu-type = "riscv,sv39";
+                     cpu0_intc: interrupt-controller {
+                             #interrupt-cells = <1>;
+                             compatible = "riscv,cpu-intc";
+                             interrupt-controller;
+                     };
+             };
+     };
+
+     soc {
+             #address-cells = <2>;
+             #size-cells = <2>;
+             compatible = "simple-bus";
+             ranges;
+
+             reset: reset-sample {
+                     compatible = "thead,reset-sample";
+                     plic-delegate = <0x0 0x101ffffc>;
+             };
+
+             clint: clint@14000000 {
+                     compatible = "riscv,clint0";
+                     interrupts-extended = <
+                             &cpu0_intc  3 &cpu0_intc  7
+                             >;
+                     reg = <0x0 0x14000000 0x0 0x04000000>;
+                     clint,has-no-64bit-mmio;
+             };
+
+             plic: interrupt-controller@10000000 {
+                     #interrupt-cells = <1>;
+                     compatible = "riscv,plic0";
+                     interrupt-controller;
+                     interrupts-extended = <
+                             &cpu0_intc  0xffffffff &cpu0_intc  9
+                             >;
+                     reg = <0x0 0x10000000 0x0 0x04000000>;
+                     reg-names = "control";
+                     riscv,max-priority = <7>;
+                     riscv,ndev = <200>;
+             };
+
+             dummy_apb: apb-clock {
+                     compatible = "fixed-clock";
+                     clock-frequency = <24000000>;

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi line 73

Quoted 5 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +5 -0

+                     clock-output-names = "dummy_apb";
+                     #clock-cells = <0>;
+             };
+
+             serial0: serial@2500000 {

This should be uart0 and board should have alias for it. Check ARM based Allwinner DTs.

Best regards,
Jernej

Quoted 11 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +11 -0

+                     compatible = "snps,dw-apb-uart";
+                     reg = <0x0 0x02500000 0x0 0x400>;
+                     reg-io-width = <4>;
+                     reg-shift = <2>;
+                     interrupt-parent = <&plic>;
+                     interrupts = <18>;
+                     clocks = <&dummy_apb>;
+                     status = "disabled";
+             };
+     };
+};

Hi!

I didn't go through all details. After you fix all comments below, you should run "make dtbs_check" and fix all reported warnings too.

Dne nedelja, 06. junij 2021 ob 11:04:07 CEST je [email protected] napisal(a):

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts

Quoted 52 lines

From: Guo Ren <[email protected]>

Add initial DTS for Allwinner D1 NeZha board having only essential devices (uart, dummy, clock, reset, clint, plic, etc).

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

---
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/allwinner/Makefile             |  2 +
 .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts  | 29 ++++++++
 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi    | 84
++++++++++++++++++++++ 4 files changed, 116 insertions(+)
 create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
 create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts

create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

arch/riscv/boot/dts/Makefile +1 -0

index fe996b8..3e7b264 100644
@@ -2,5 +2,6 @@
 subdir-y += sifive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
 subdir-y += microchip
+subdir-y += allwinner
 
 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/Makefile new file mode 100644 index 00000000..4adbf4b

arch/riscv/boot/dts/allwinner/Makefile new file +2 -0

@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SUNXI) += allwinner-d1-nezha-kit.dtb

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file mode 100644
index 00000000..cd9f7c9

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +0 -0

Board DT names are comprised of soc name and board name, in this case it would be "sun20i-d1-nezha-kit.dts"

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 1

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +1 -0

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

Usually copyrights are added below spdx id.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 9

Quoted 8 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +8 -0

+
+/dts-v1/;
+
+#include "allwinner-d1.dtsi"
+
+/ {
+     #address-cells = <2>;
+     #size-cells = <2>;

This should be part of SoC level DTSI.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 11

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +2 -0

+     model = "Allwinner D1 NeZha Kit";
+     compatible = "allwinner,d1-nezha-kit";

Board specific compatible string should be followed with SoC compatible, in this case "allwinner,sun20i-d1". You should document it too.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 14

Quoted 3 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +3 -0

+
+     chosen {
+             bootargs = "console=ttyS0,115200";

Above line doesn't belong here. If anything, it should be added dynamically by bootloader.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 21

Quoted 8 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +7 -0

+             stdout-path = &serial0;
+     };
+
+     memory@40000000 {
+             device_type = "memory";
+             reg = <0x0 0x40000000 0x0 0x20000000>;
+     };

Ditto for whole memory node.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 24

Quoted 4 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +3 -0

+
+     soc {
+     };

There is no point having empty nodes.

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

Quoted 10 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +5 -0

+};
+
+&serial0 {
+     status = "okay";
+};

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file mode 100644 index 00000000..11cd938

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +0 -0

Current naming approach for Allwinner SoC level DTSI is "sun20i-d1.dtsi".

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi line 7

Quoted 9 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +7 -0

@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
 
+
+/dts-v1/;
+
+/ {
+     #address-cells = <2>;
+     #size-cells = <2>;

Since all peripherals and memory are below 4 GiB, why have 64-bit addresses and sizes? It just clutters DT.

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi line 9

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +2 -0

+     model = "Allwinner D1 Soc";
+     compatible = "allwinner,d1-nezha-kit";

Compatible and model don't belong to SoC level DTSI.

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

Quoted 3 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +3 -0

+
+     chosen {
+     };

Remove empty node.

Quoted 51 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +51 -0

+
+     cpus {
+             #address-cells = <1>;
+             #size-cells = <0>;
+             timebase-frequency = <2400000>;
+             cpu@0 {
+                     device_type = "cpu";
+                     reg = <0>;
+                     status = "okay";
+                     compatible = "riscv";
+                     riscv,isa = "rv64imafdcv";
+                     mmu-type = "riscv,sv39";
+                     cpu0_intc: interrupt-controller {
+                             #interrupt-cells = <1>;
+                             compatible = "riscv,cpu-intc";
+                             interrupt-controller;
+                     };
+             };
+     };
+
+     soc {
+             #address-cells = <2>;
+             #size-cells = <2>;
+             compatible = "simple-bus";
+             ranges;
+
+             reset: reset-sample {
+                     compatible = "thead,reset-sample";
+                     plic-delegate = <0x0 0x101ffffc>;
+             };
+
+             clint: clint@14000000 {
+                     compatible = "riscv,clint0";
+                     interrupts-extended = <
+                             &cpu0_intc  3 &cpu0_intc  7
+                             >;
+                     reg = <0x0 0x14000000 0x0 0x04000000>;
+                     clint,has-no-64bit-mmio;
+             };
+
+             plic: interrupt-controller@10000000 {
+                     #interrupt-cells = <1>;
+                     compatible = "riscv,plic0";
+                     interrupt-controller;
+                     interrupts-extended = <
+                             &cpu0_intc  0xffffffff &cpu0_intc  9
+                             >;
+                     reg = <0x0 0x10000000 0x0 0x04000000>;
+                     reg-names = "control";
+                     riscv,max-priority = <7>;
+                     riscv,ndev = <200>;

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi line 73

Quoted 10 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +10 -0

+             };
+
+             dummy_apb: apb-clock {
+                     compatible = "fixed-clock";
+                     clock-frequency = <24000000>;
+                     clock-output-names = "dummy_apb";
+                     #clock-cells = <0>;
+             };
+
+             serial0: serial@2500000 {

This should be uart0 and board should have alias for it. Check ARM based Allwinner DTs.

Best regards,
Jernej

Quoted 11 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +11 -0

+                     compatible = "snps,dw-apb-uart";
+                     reg = <0x0 0x02500000 0x0 0x400>;
+                     reg-io-width = <4>;
+                     reg-shift = <2>;
+                     interrupt-parent = <&plic>;
+                     interrupts = <18>;
+                     clocks = <&dummy_apb>;
+                     status = "disabled";
+             };
+     };
+};

Quoted 85 lines · Jernej Škrabec

Hi!

I didn't go through all details. After you fix all comments below, you should run "make dtbs_check" and fix all reported warnings too.

Dne nedelja, 06. junij 2021 ob 11:04:07 CEST je [email protected] napisal(a):

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts

Quoted 52 lines

From: Guo Ren <[email protected]>

Add initial DTS for Allwinner D1 NeZha board having only essential devices (uart, dummy, clock, reset, clint, plic, etc).

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

---
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/allwinner/Makefile             |  2 +
 .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts  | 29 ++++++++
 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi    | 84
++++++++++++++++++++++ 4 files changed, 116 insertions(+)
 create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
 create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts

create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

arch/riscv/boot/dts/Makefile +1 -0

index fe996b8..3e7b264 100644
@@ -2,5 +2,6 @@
 subdir-y += sifive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
 subdir-y += microchip
+subdir-y += allwinner
 
 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/Makefile new file mode 100644 index 00000000..4adbf4b

arch/riscv/boot/dts/allwinner/Makefile new file +2 -0

@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SUNXI) += allwinner-d1-nezha-kit.dtb

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file mode 100644
index 00000000..cd9f7c9

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +0 -0

Board DT names are comprised of soc name and board name, in this case it would be "sun20i-d1-nezha-kit.dts"

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 1

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +1 -0

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

Usually copyrights are added below spdx id.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 9

Quoted 8 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +8 -0

+
+/dts-v1/;
+
+#include "allwinner-d1.dtsi"
+
+/ {
+     #address-cells = <2>;
+     #size-cells = <2>;

This should be part of SoC level DTSI.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 11

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +2 -0

+     model = "Allwinner D1 NeZha Kit";
+     compatible = "allwinner,d1-nezha-kit";

Board specific compatible string should be followed with SoC compatible, in this case "allwinner,sun20i-d1". You should document it too.

Quoted 6 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 14

Quoted 3 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +3 -0

+
+     chosen {
+             bootargs = "console=ttyS0,115200";

Above line doesn't belong here. If anything, it should be added dynamically by bootloader.

After discussion, we still want to keep a default value here. Sometimes we could boot with jtag and parse dtb is hard for gdbinit script.

Quoted 9 lines

Quoted 8 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +7 -0

+             stdout-path = &serial0;
+     };
+
+     memory@40000000 {
+             device_type = "memory";
+             reg = <0x0 0x40000000 0x0 0x20000000>;
+     };

Quoted 1 line

Ditto for whole memory node.

Ditto

Quoted 106 lines · Guo Ren

Quoted 85 lines · Jernej Škrabec

Hi!

I didn't go through all details. After you fix all comments below, you should run "make dtbs_check" and fix all reported warnings too.

Dne nedelja, 06. junij 2021 ob 11:04:07 CEST je [email protected] napisal(a):

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts

Quoted 52 lines

From: Guo Ren <[email protected]>

Add initial DTS for Allwinner D1 NeZha board having only essential devices (uart, dummy, clock, reset, clint, plic, etc).

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

---
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/allwinner/Makefile             |  2 +
 .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts  | 29 ++++++++
 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi    | 84
++++++++++++++++++++++ 4 files changed, 116 insertions(+)
 create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
 create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts

create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

arch/riscv/boot/dts/Makefile +1 -0

index fe996b8..3e7b264 100644
@@ -2,5 +2,6 @@
 subdir-y += sifive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
 subdir-y += microchip
+subdir-y += allwinner
 
 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/Makefile new file mode 100644 index 00000000..4adbf4b

arch/riscv/boot/dts/allwinner/Makefile new file +2 -0

@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SUNXI) += allwinner-d1-nezha-kit.dtb

(quoted diff) +0 -0

b/arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file mode 100644
index 00000000..cd9f7c9

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +0 -0

Board DT names are comprised of soc name and board name, in this case it would be "sun20i-d1-nezha-kit.dts"

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 1

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +1 -0

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

Usually copyrights are added below spdx id.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 9

Quoted 8 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +8 -0

+
+/dts-v1/;
+
+#include "allwinner-d1.dtsi"
+
+/ {
+     #address-cells = <2>;
+     #size-cells = <2>;

This should be part of SoC level DTSI.

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 11

Quoted 2 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +2 -0

+     model = "Allwinner D1 NeZha Kit";
+     compatible = "allwinner,d1-nezha-kit";

Board specific compatible string should be followed with SoC compatible, in this case "allwinner,sun20i-d1". You should document it too.

Quoted 6 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts line 14

Quoted 3 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +3 -0

+
+     chosen {
+             bootargs = "console=ttyS0,115200";

Above line doesn't belong here. If anything, it should be added dynamically by bootloader.

After discussion, we still want to keep a default value here. Sometimes we could boot with jtag and parse dtb is hard for gdbinit script.

Quoted 9 lines

Quoted 8 lines

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +7 -0

+             stdout-path = &serial0;
+     };
+
+     memory@40000000 {
+             device_type = "memory";
+             reg = <0x0 0x40000000 0x0 0x20000000>;
+     };

Quoted 3 lines

Quoted 1 line

Ditto for whole memory node.

Ditto

The thing is that there's never a good value for a default. Let's take the memory node here: what would be a good default? If we want to make it work everywhere it's going to be the lowest amount of memory available on the D1 boards. It's going to be hard to maintain and very likely to be overlooked, resulting in broken boards anyway.

If someone is savvy enough to use JTAG, it's not really difficult to modify the DT for their board when they need it.

Maxime

From: Guo Ren <[email protected]>

Add initial DTS for Allwinner D1 NeZha board having only essential devices (uart, dummy, clock, reset, clint, plic, etc).

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

---
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/allwinner/Makefile             |  2 +
 .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts  | 29 ++++++++
 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi    | 84 ++++++++++++++++++++++

 4 files changed, 116 insertions(+)
 create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
 create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
 create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

arch/riscv/boot/dts/Makefile +0 -0

index fe996b8..3e7b264 100644

arch/riscv/boot/dts/Makefile +0 -0

 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

arch/riscv/boot/dts/allwinner/Makefile new file +2 -0

new file mode 100644
index 00000000..4adbf4b
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SUNXI) += allwinner-d1-nezha-kit.dtb

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +29 -0

new file mode 100644
index 00000000..cd9f7c9
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "allwinner-d1.dtsi"
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Allwinner D1 NeZha Kit";
+	compatible = "allwinner,d1-nezha-kit";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = &serial0;
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x20000000>;
+	};
+
+	soc {
+	};
+};
+
+&serial0 {
+	status = "okay";
+};

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +32 -0

new file mode 100644
index 00000000..11cd938
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Allwinner D1 Soc";
+	compatible = "allwinner,d1-nezha-kit";
+
+	chosen {
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <2400000>;
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv64imafdcv";
+			mmu-type = "riscv,sv39";
+			cpu0_intc: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+

Hi,

Thanks for the patches

Quoted 17 lines · On Sun, Jun 06, 2021 at 09:04:07AM +0000, [email protected] wrote:

From: Guo Ren <[email protected]>

Add initial DTS for Allwinner D1 NeZha board having only essential devices (uart, dummy, clock, reset, clint, plic, etc).

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

Quoted 5 lines

---
 arch/riscv/boot/dts/Makefile                       |  1 +
 arch/riscv/boot/dts/allwinner/Makefile             |  2 +
 .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts  | 29 ++++++++
 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi    | 84 ++++++++++++++++++++++

Can you add the riscv folder to our MAINTAINERS entry as well?

Quoted 6 lines

 4 files changed, 116 insertions(+)
 create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
 create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
 create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi

arch/riscv/boot/dts/Makefile line 5

Quoted 9 lines

arch/riscv/boot/dts/Makefile +1 -0

index fe996b8..3e7b264 100644
@@ -2,5 +2,6 @@
 subdir-y += sifive
 subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
 subdir-y += microchip
+subdir-y += allwinner

I assume they should be ordered alphabetically?

Quoted 87 lines

arch/riscv/boot/dts/Makefile +0 -0

 obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

arch/riscv/boot/dts/allwinner/Makefile new file +2 -0

new file mode 100644
index 00000000..4adbf4b
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_SOC_SUNXI) += allwinner-d1-nezha-kit.dtb

arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts new file +29 -0

new file mode 100644
index 00000000..cd9f7c9
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "allwinner-d1.dtsi"
+
+/ {
+     #address-cells = <2>;
+     #size-cells = <2>;
+     model = "Allwinner D1 NeZha Kit";
+     compatible = "allwinner,d1-nezha-kit";
+
+     chosen {
+             bootargs = "console=ttyS0,115200";
+             stdout-path = &serial0;
+     };
+
+     memory@40000000 {
+             device_type = "memory";
+             reg = <0x0 0x40000000 0x0 0x20000000>;
+     };
+
+     soc {
+     };
+};
+
+&serial0 {
+     status = "okay";
+};

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +36 -0

new file mode 100644
index 00000000..11cd938
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+/ {
+     #address-cells = <2>;
+     #size-cells = <2>;
+     model = "Allwinner D1 Soc";
+     compatible = "allwinner,d1-nezha-kit";
+
+     chosen {
+     };
+
+     cpus {
+             #address-cells = <1>;
+             #size-cells = <0>;
+             timebase-frequency = <2400000>;
+             cpu@0 {
+                     device_type = "cpu";
+                     reg = <0>;
+                     status = "okay";
+                     compatible = "riscv";
+                     riscv,isa = "rv64imafdcv";
+                     mmu-type = "riscv,sv39";
+                     cpu0_intc: interrupt-controller {
+                             #interrupt-cells = <1>;
+                             compatible = "riscv,cpu-intc";
+                             interrupt-controller;
+                     };
+             };
+     };
+
+     soc {
+             #address-cells = <2>;
+             #size-cells = <2>;
+             compatible = "simple-bus";

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi line 42

Quoted 6 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +6 -0

+             ranges;
+
+             reset: reset-sample {
+                     compatible = "thead,reset-sample";
+                     plic-delegate = <0x0 0x101ffffc>;
+             };

This compatible is not documented anywhere?

Maxime

Quoted 6 lines · Maxime Ripard

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi line 42

Quoted 4 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +4 -0

+             reset: reset-sample {
+                     compatible = "thead,reset-sample";
+                     plic-delegate = <0x0 0x101ffffc>;
+             };

This compatible is not documented anywhere?

It used by opensbi (riscv runtime firmware), not in Linux. But I think we should keep it.

Quoted 6 lines · Guo Ren

Quoted 5 lines · Maxime Ripard

Quoted 4 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +4 -0

+             reset: reset-sample {
+                     compatible = "thead,reset-sample";
+                     plic-delegate = <0x0 0x101ffffc>;
+             };

Quoted 4 lines

Quoted 1 line

This compatible is not documented anywhere?

It used by opensbi (riscv runtime firmware), not in Linux. But I think we should keep it.

This should have a documentation still.

Maxime

Quoted 8 lines · Guo Ren

Quoted 6 lines · Maxime Ripard

Quoted 5 lines

Quoted 4 lines

arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi new file +4 -0

+             reset: reset-sample {
+                     compatible = "thead,reset-sample";
+                     plic-delegate = <0x0 0x101ffffc>;
+             };

Quoted 6 lines

Quoted 4 lines

Quoted 1 line

This compatible is not documented anywhere?

It used by opensbi (riscv runtime firmware), not in Linux. But I think we should keep it.

This should have a documentation still.

Could we detail the above in [1]?

1: https://github.com/riscv/opensbi/blob/master/docs/platform/thead-c9xx.md

Quoted 2 lines

Maxime

Signature · 4 lines

Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

From: Guo Ren <[email protected]>

Add Allwinner kconfig option which selects SoC specific and common drivers that is required for this SoC.

Allwinner D1 uses custom PTE attributes to solve non-coherency SOC interconnect issues for dma synchronization, so we set the default value when SOC_SUNXI selected.

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

---
 arch/riscv/Kconfig.socs      | 12 ++++++++++++
 arch/riscv/configs/defconfig |  1 +
 2 files changed, 13 insertions(+)

arch/riscv/Kconfig.socs +2 -0

index ed96376..055fb3e 100644
@@ -69,4 +69,16 @@ config SOC_CANAAN_K210_DTB_SOURCE
 
 endif
 
+config SOC_SUNXI
+	bool "Allwinner SoCs"

Quoted 8 lines · On Sun, Jun 06, 2021 at 09:04:08AM +0000, [email protected] wrote:

arch/riscv/Kconfig.socs +0 -0

index ed96376..055fb3e 100644
@@ -69,4 +69,16 @@ config SOC_CANAAN_K210_DTB_SOURCE
 
 endif
 

arch/riscv/Kconfig.socs config SOC_CANAAN_K210_DTB_SOURCE · line 83

Quoted 12 lines

arch/riscv/Kconfig.socs +12 -0

+config SOC_SUNXI
+     bool "Allwinner SoCs"
+     depends on MMU
+     select DWMAC_GENERIC
+     select SERIAL_8250
+     select SERIAL_8250_CONSOLE
+     select SERIAL_8250_DW
+     select SIFIVE_PLIC
+     select STMMAC_ETH
+     help
+       This enables support for Allwinner SoC platforms like the D1.
+

We probably don't want to select DWMAC, STMMAC_ETH and the 8250 options, looks good otherwise.

Quoted 10 lines · Maxime Ripard

Quoted 8 lines · On Sun, Jun 06, 2021 at 09:04:08AM +0000, [email protected] wrote:

arch/riscv/Kconfig.socs +0 -0

index ed96376..055fb3e 100644
@@ -69,4 +69,16 @@ config SOC_CANAAN_K210_DTB_SOURCE
 
 endif
 

Quoted 15 lines

arch/riscv/Kconfig.socs config SOC_CANAAN_K210_DTB_SOURCE · line 83

Quoted 12 lines

arch/riscv/Kconfig.socs +12 -0

+config SOC_SUNXI
+     bool "Allwinner SoCs"
+     depends on MMU
+     select DWMAC_GENERIC
+     select SERIAL_8250
+     select SERIAL_8250_CONSOLE
+     select SERIAL_8250_DW
+     select SIFIVE_PLIC
+     select STMMAC_ETH
+     help
+       This enables support for Allwinner SoC platforms like the D1.
+

We probably don't want to select DWMAC, STMMAC_ETH and the 8250 options, looks good otherwise.

Correct: those subsystems may be completely disabled, which would lead to a build failure, and a platform should not force-enable drivers or subsystems unless
those are build time dependencies.

Arnd

Hi,

Quoted 36 lines · On Sun, Jun 06, 2021 at 09:04:08AM +0000, [email protected] wrote:

From: Guo Ren <[email protected]>

Add Allwinner kconfig option which selects SoC specific and common drivers that is required for this SoC.

Allwinner D1 uses custom PTE attributes to solve non-coherency SOC interconnect issues for dma synchronization, so we set the default value when SOC_SUNXI selected.

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

---
 arch/riscv/Kconfig.socs      | 12 ++++++++++++
 arch/riscv/configs/defconfig |  1 +
 2 files changed, 13 insertions(+)

arch/riscv/Kconfig.socs +2 -0

index ed96376..055fb3e 100644
@@ -69,4 +69,16 @@ config SOC_CANAAN_K210_DTB_SOURCE
 
 endif
 
+config SOC_SUNXI
+     bool "Allwinner SoCs"

arch/riscv/Kconfig.socs config SOC_CANAAN_K210_DTB_SOURCE · line 83

Quoted 10 lines

arch/riscv/Kconfig.socs +10 -0

+     depends on MMU
+     select DWMAC_GENERIC
+     select SERIAL_8250
+     select SERIAL_8250_CONSOLE
+     select SERIAL_8250_DW
+     select SIFIVE_PLIC
+     select STMMAC_ETH
+     help
+       This enables support for Allwinner SoC platforms like the D1.
+

We probably don't want to select DWMAC, STMMAC_ETH and the 8250 options, looks good otherwise.

Maxime

Quoted 54 lines · Maxime Ripard

Hi,

Quoted 36 lines · On Sun, Jun 06, 2021 at 09:04:08AM +0000, [email protected] wrote:

From: Guo Ren <[email protected]>

Add Allwinner kconfig option which selects SoC specific and common drivers that is required for this SoC.

Allwinner D1 uses custom PTE attributes to solve non-coherency SOC interconnect issues for dma synchronization, so we set the default value when SOC_SUNXI selected.

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

---
 arch/riscv/Kconfig.socs      | 12 ++++++++++++
 arch/riscv/configs/defconfig |  1 +
 2 files changed, 13 insertions(+)

arch/riscv/Kconfig.socs +2 -0

index ed96376..055fb3e 100644
@@ -69,4 +69,16 @@ config SOC_CANAAN_K210_DTB_SOURCE
 
 endif
 
+config SOC_SUNXI
+     bool "Allwinner SoCs"

arch/riscv/Kconfig.socs config SOC_CANAAN_K210_DTB_SOURCE · line 83

Quoted 10 lines

arch/riscv/Kconfig.socs +10 -0

+     depends on MMU
+     select DWMAC_GENERIC
+     select SERIAL_8250
+     select SERIAL_8250_CONSOLE
+     select SERIAL_8250_DW
+     select SIFIVE_PLIC
+     select STMMAC_ETH
+     help
+       This enables support for Allwinner SoC platforms like the D1.
+

We probably don't want to select DWMAC, STMMAC_ETH and the 8250 options, looks good otherwise.

Quoted 1 line

Maxime

Remove DWMAC, STMMAC_ETH is okay.

But I think we still need:
select SERIAL_8250_DW if SERIAL_8250

Quoted 55 lines · Guo Ren

Quoted 54 lines · Maxime Ripard

Hi,

Quoted 36 lines · On Sun, Jun 06, 2021 at 09:04:08AM +0000, [email protected] wrote:

From: Guo Ren <[email protected]>

Add Allwinner kconfig option which selects SoC specific and common drivers that is required for this SoC.

Allwinner D1 uses custom PTE attributes to solve non-coherency SOC interconnect issues for dma synchronization, so we set the default value when SOC_SUNXI selected.

Signed-off-by Guo Ren <[email protected]>

Co-Developed-by Liu Shaohua <[email protected]>

Signed-off-by Liu Shaohua <[email protected]>

Cc Anup Patel <[email protected]>

Cc Atish Patra <[email protected]>

Cc Christoph Hellwig <[email protected]>

Cc Chen-Yu Tsai <[email protected]>

Cc Drew Fustini <[email protected]>

Cc Maxime Ripard <[email protected]>

Cc Palmer Dabbelt <[email protected]>

Cc Wei Fu <[email protected]>

Cc Wei Wu <[email protected]>

---
 arch/riscv/Kconfig.socs      | 12 ++++++++++++
 arch/riscv/configs/defconfig |  1 +
 2 files changed, 13 insertions(+)

arch/riscv/Kconfig.socs +2 -0

index ed96376..055fb3e 100644
@@ -69,4 +69,16 @@ config SOC_CANAAN_K210_DTB_SOURCE
 
 endif
 
+config SOC_SUNXI
+     bool "Allwinner SoCs"

arch/riscv/Kconfig.socs config SOC_CANAAN_K210_DTB_SOURCE · line 83

Quoted 10 lines

arch/riscv/Kconfig.socs +10 -0

+     depends on MMU
+     select DWMAC_GENERIC
+     select SERIAL_8250
+     select SERIAL_8250_CONSOLE
+     select SERIAL_8250_DW
+     select SIFIVE_PLIC
+     select STMMAC_ETH
+     help
+       This enables support for Allwinner SoC platforms like the D1.
+

We probably don't want to select DWMAC, STMMAC_ETH and the 8250 options, looks good otherwise.