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FAILED: patch "[PATCH] clk: agilex/stratix10: add support for the 2nd bypass" failed to apply to 5.10-stable tree

PATCH [email protected] 1 participant 1 message Jul 11, 2021

Subsystems (3)
Stable branch Common clk Arm/socfpga clock framework support
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The patch below does not apply to the 5.10-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From c2c9c5661a48bf2e67dcb4e989003144304acd6a Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <[email protected]>
Date: Thu, 10 Jun 2021 21:52:00 -0500
Subject: [PATCH] clk: agilex/stratix10: add support for the 2nd bypass

The EMAC clocks on Stratix10/Agilex/N5X have an additional bypass that was not being accounted for. The bypass selects between emaca_clk/emacb_clk and boot_clk.

Because the bypass register offset is different between Stratix10 and Agilex/N5X, it's best to create a new function to calculate the bypass.

Fixes 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc [email protected]
Signed-off-by Dinh Nguyen <[email protected]>
Link https://lore.kernel.org/r/[email protected] open here
Signed-off-by Stephen Boyd <[email protected]>
drivers/clk/socfpga/clk-agilex.c +3 -1
index edfa87d0cd76..1cb21ea79c64 100644
@@ -177,6 +177,8 @@ static const struct clk_parent_data emac_mux[] = {
 	  .name = "emaca_free_clk", },
 	{ .fw_name = "emacb_free_clk",
 	  .name = "emacb_free_clk", },
+	{ .fw_name = "boot_clk",
+	  .name = "boot_clk", },
 };
 
 static const struct clk_parent_data noc_mux[] = {

@@ -399,7 +401,7 @@ static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks,
 	int i;
 
 	for (i = 0; i < nums; i++) {
-		hw_clk = s10_register_gate(&clks[i], base);
+		hw_clk = agilex_register_gate(&clks[i], base);
 		if (IS_ERR(hw_clk)) {
 			pr_err("%s: failed to register clock %s\n",
 			       __func__, clks[i].name);
drivers/clk/socfpga/clk-gate-s10.c +118 -1

147 lines not on this page · raw message

drivers/clk/socfpga/stratix10-clk.h +2 -0
index 61eaf3a41fbb..75234e0783e1 100644
@@ -85,4 +85,6 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c
 				    void __iomem *reg);
 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
 			      void __iomem *reg);
+struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
+			      void __iomem *reg);
 #endif	/* __STRATIX10_CLK_H */