scsi: ufs: ufs-mediatek: Change dbg select by check hw version

PATCH Superseded [email protected] 2 participants 5 messages Aug 30, 2021 – Sep 1, 2021

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SCSI Arm MediaTek

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[email protected]

author

2021-08-30 12:11 UTC #0 lore raw

PATCH 1/1 scsi: ufs: ufs-mediatek: Change dbg select by check hw version

From: Peter Wang <[email protected]>

Mediatek UFS dbg select setting is changed in new HW version. This patch check the HW version before set dbg select.

Signed-off-by Peter Wang <[email protected]>

---
 drivers/scsi/ufs/ufs-mediatek.c |   22 ++++++++++++++++++++--
 drivers/scsi/ufs/ufs-mediatek.h |    4 ++++
 2 files changed, 24 insertions(+), 2 deletions(-)

drivers/scsi/ufs/ufs-mediatek.c +20 -2

index d2c2516..c7c18d8 100644
@@ -296,6 +296,24 @@ static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba,
 	host->ref_clk_ungating_wait_us = ungating_us;
 }
 
+static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
+{
+	static u32 hw_ver;
+
+	if (!hw_ver)
+		hw_ver = ufshcd_readl(hba, REG_UFS_MTK_HW_VER);
+
+	if (((hw_ver >> 16) & 0xFF) >= 0x36) {
+		ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
+		ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
+		ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
+		ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2);
+		ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3);
+	} else {
+		ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
+	}
+}
+
 static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
 				   unsigned long max_wait_ms)
 {

@@ -305,7 +323,7 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
 	timeout = ktime_add_ms(ktime_get(), max_wait_ms);
 	do {
 		time_checked = ktime_get();
-		ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
+		ufs_mtk_dbg_sel(hba);
 		val = ufshcd_readl(hba, REG_UFS_PROBE);
 		val = val >> 28;

@@ -1001,7 +1019,7 @@ static void ufs_mtk_dbg_register_dump(struct ufs_hba *hba)
 			 "MPHY Ctrl ");
 
 	/* Direct debugging information to REG_MTK_PROBE */
-	ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
+	ufs_mtk_dbg_sel(hba);
 	ufshcd_dump_regs(hba, REG_UFS_PROBE, 0x4, "Debug Probe ");
 }

drivers/scsi/ufs/ufs-mediatek.h +4 -0

index 3f0d3bb..10da6e3 100644
@@ -18,6 +18,10 @@
 #define REG_UFS_REJECT_MON          0x22AC
 #define REG_UFS_DEBUG_SEL           0x22C0
 #define REG_UFS_PROBE               0x22C8
+#define REG_UFS_DEBUG_SEL_B0        0x22D0
+#define REG_UFS_DEBUG_SEL_B1        0x22D4
+#define REG_UFS_DEBUG_SEL_B2        0x22D8
+#define REG_UFS_DEBUG_SEL_B3        0x22DC
 
 /*
  * Ref-clk control

Signature · 1 line

1.7.9.5

Bart Van Assche

2021-08-31 02:47 UTC #1 lore raw

Quoted 7 lines · On 8/30/21 05:11, [email protected] wrote:

drivers/scsi/ufs/ufs-mediatek.c +7 -0

+static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
+{
+	static u32 hw_ver;
+
+	if (!hw_ver)
+		hw_ver = ufshcd_readl(hba, REG_UFS_MTK_HW_VER);
+

drivers/scsi/ufs/ufs-mediatek.c static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba, · line 315

Quoted 10 lines

drivers/scsi/ufs/ufs-mediatek.c +10 -0

+	if (((hw_ver >> 16) & 0xFF) >= 0x36) {
+		ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
+		ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
+		ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
+		ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2);
+		ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3);
+	} else {
+		ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
+	}
+}

Can ufs_mtk_dbg_sel() be called from multiple threads at the same time? Does the 'hw_ver' variable need to be protected against concurrent writes?

Thanks,

Bart.

Peter Wang

author

2021-09-01 02:29 UTC #2 lore raw

Hi Bart,

REG_UFS_MTK_HW_VER is a read only mediatek dedicated register. So, hw_ver will get a const value for mediatek to decide how to use debug select. It only need read once, no need multi-threads protected.

Thanks
Peter

Quoted 27 lines · Bart Van Assche

Quoted 7 lines · On 8/30/21 05:11, [email protected] wrote:
drivers/scsi/ufs/ufs-mediatek.c +7 -0
+static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
+{
+	static u32 hw_ver;
+
+	if (!hw_ver)
+		hw_ver = ufshcd_readl(hba, REG_UFS_MTK_HW_VER);
+
drivers/scsi/ufs/ufs-mediatek.c static void ufs_mtk_setup_ref_clk_wait_us(struct ufs_hba *hba, · line 315
Quoted 10 lines
drivers/scsi/ufs/ufs-mediatek.c +10 -0
+	if (((hw_ver >> 16) & 0xFF) >= 0x36) {
+		ufshcd_writel(hba, 0x820820, REG_UFS_DEBUG_SEL);
+		ufshcd_writel(hba, 0x0, REG_UFS_DEBUG_SEL_B0);
+		ufshcd_writel(hba, 0x55555555, REG_UFS_DEBUG_SEL_B1);
+		ufshcd_writel(hba, 0xaaaaaaaa, REG_UFS_DEBUG_SEL_B2);
+		ufshcd_writel(hba, 0xffffffff, REG_UFS_DEBUG_SEL_B3);
+	} else {
+		ufshcd_writel(hba, 0x20, REG_UFS_DEBUG_SEL);
+	}
+}
Can ufs_mtk_dbg_sel() be called from multiple threads at the same time?
Does the 'hw_ver' variable need to be protected against concurrent writes?
Thanks,
Bart.

Bart Van Assche

2021-09-01 02:56 UTC #3 lore raw

Quoted 3 lines · Peter Wang

REG_UFS_MTK_HW_VER is a read only mediatek dedicated register. So, hw_ver will get a const value for mediatek to decide how to use debug select. It only need read once, no need multi-threads protected.

Hi Peter,

The above can be concluded easily by a human but not by software. If this code is analyzed with KCSAN then KCSAN will probably complain. See also Documentation/dev-tools/kcsan.rst.

Anyway, I'm fine with this patch.

Thanks,

Bart.

Peter Wang

author

2021-09-01 05:46 UTC #4 lore raw

Hi Bart,

Really appreciate your reminder.
We will upload new patch to bypss KCSAN.
Thank you very much.

Peter

Quoted 18 lines · Bart Van Assche

Quoted 4 lines · Peter Wang
REG_UFS_MTK_HW_VER is a read only mediatek dedicated register. So, hw_ver will get a const value for mediatek to decide how to use debug select. It only need read once, no need multi-threads protected.
Hi Peter,
The above can be concluded easily by a human but not by software. If this code is analyzed with KCSAN then KCSAN will probably complain. See
also Documentation/dev-tools/kcsan.rst.
Anyway, I'm fine with this patch.
Thanks,
Bart.