FAILED: patch "[PATCH] net: axienet: Wait for PhyRstCmplt after core reset" failed to apply to 5.4-stable tree
[email protected]
maintainerThe patch below does not apply to the 5.4-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From b400c2f4f4c53c86594dd57098970d97d488bfde Mon Sep 17 00:00:00 2001
From: Robert Hancock <[email protected]>
Date: Tue, 18 Jan 2022 15:41:25 -0600
Subject: [PATCH] net: axienet: Wait for PhyRstCmplt after core reset
When resetting the device, wait for the PhyRstCmplt bit to be set in the interrupt status register before continuing initialization, to ensure that the core is actually ready. When using an external PHY, this also ensures we do not start trying to access the PHY while it is still in reset. The PHY reset is initiated by the core reset which is triggered just above, but remains asserted for 5ms after the core is reset according to the documentation.
The MgtRdy bit could also be waited for, but unfortunately when using 7-series devices, the bit does not appear to work as documented (it seems to behave as some sort of link state indication and not just an indication the transceiver is ready) so it can't really be relied on for this purpose.
drivers/net/ethernet/xilinx/xilinx_axienet_main.c +10 -0
@@ -516,6 +516,16 @@ static int __axienet_device_reset(struct axienet_local *lp)return ret; } +/* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has finished */ + ret =read_poll_timeout (axienet_ior, value, + value &XAE_INT_PHYRSTCMPLT_MASK , +DELAY_OF_ONE_MILLISEC ,50000 , false, lp, +XAE_IS_OFFSET ); +if (ret) { +dev_err (lp->dev,"%s: timeout waiting for PhyRstCmplt\n" , __func__); +return ret; + } +return 0 ; }