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FAILED: patch "[PATCH] drm/amd/display: Wrap dcn301_calculate_wm_and_dlg for FPU." failed to apply to 5.15-stable tree

PATCH [email protected] 1 participant 1 message Mar 7, 2022

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Stable branch DRM drivers Radeon and amdgpu DRM drivers AMD display core +1 more subsystems
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The patch below does not apply to the 5.15-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 25f1488bdbba63415239ff301fe61a8546140d9f Mon Sep 17 00:00:00 2001
From: Bas Nieuwenhuizen <[email protected]>
Date: Mon, 24 Jan 2022 01:23:36 +0100
Subject: [PATCH] drm/amd/display: Wrap dcn301_calculate_wm_and_dlg for FPU.

Mirrors the logic for dcn30. Cue lots of WARNs and some kernel panics without this fix.

Cc [email protected]
Signed-off-by Bas Nieuwenhuizen <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c +11 -0
index b4001233867c..5d9637b07429 100644
@@ -1380,6 +1380,17 @@ static void set_wm_ranges(
 	pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
 }
 
+static void dcn301_calculate_wm_and_dlg(
+		struct dc *dc, struct dc_state *context,
+		display_e2e_pipe_params_st *pipes,
+		int pipe_cnt,
+		int vlevel)
+{
+	DC_FP_START();
+	dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
+	DC_FP_END();
+}
+
 static struct resource_funcs dcn301_res_pool_funcs = {
 	.destroy = dcn301_destroy_resource_pool,
 	.link_enc_create = dcn301_link_encoder_create,
drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c +1 -1
index 94c32832a0e7..0a7a33864973 100644
@@ -327,7 +327,7 @@ void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)
 		dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
 }
 
-void dcn301_calculate_wm_and_dlg(struct dc *dc,
+void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,
 		struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
 		int pipe_cnt,
drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h +1 -1
index fc7065d17842..774b0fdfc80b 100644
@@ -34,7 +34,7 @@ void dcn301_fpu_set_wm_ranges(int i,
 
 void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info);
 
-void dcn301_calculate_wm_and_dlg(struct dc *dc,
+void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,
 		struct dc_state *context,
 		display_e2e_pipe_params_st *pipes,
 		int pipe_cnt,