Linux 5.4.199
Greg Kroah-Hartman
maintainerI'm announcing the release of the 5.4.199 kernel.
All users of the 5.4 kernel series must upgrade.
The updated 5.4.y git tree can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git linux-5.4.y
and can be browsed at the normal kernel.org git web browser:
https://git.kernel.org/?p=linux/kernel/git/stable/linux-stable.git;a=summary
thanks,
greg k-h
------------
Documentation/ABI/testing/sysfs-devices-system-cpu | 1 Documentation/admin-guide/hw-vuln/index.rst | 1 Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst | 246 ++++++++++ Documentation/admin-guide/kernel-parameters.txt | 36 + Makefile | 2 arch/x86/include/asm/cpufeatures.h | 1 arch/x86/include/asm/intel-family.h | 9 arch/x86/include/asm/msr-index.h | 25 + arch/x86/include/asm/nospec-branch.h | 2 arch/x86/kernel/cpu/bugs.c | 235 ++++++++- arch/x86/kernel/cpu/common.c | 52 +- arch/x86/kvm/vmx/vmx.c | 75 +++ arch/x86/kvm/vmx/vmx.h | 3 arch/x86/kvm/x86.c | 4 drivers/base/cpu.c | 8 include/linux/cpu.h | 4 16 files changed, 663 insertions(+), 41 deletions(-)
Gayatri Kammela (1):
x86/cpu: Add another Alder Lake CPU to the Intel family
Greg Kroah-Hartman (1):
Linux 5.4.199
Guenter Roeck (1):
cpu/speculation: Add prototype for cpu_show_srbds()
Josh Poimboeuf (1):
x86/speculation/mmio: Print SMT warning
Pawan Gupta (10):
Documentation: Add documentation for Processor MMIO Stale Data x86/speculation/mmio: Enumerate Processor MMIO Stale Data bug x86/speculation: Add a common function for MD_CLEAR mitigation update x86/speculation/mmio: Add mitigation for Processor MMIO Stale Data x86/bugs: Group MDS, TAA & Processor MMIO Stale Data mitigations x86/speculation/mmio: Enable CPU Fill buffer clearing on idle x86/speculation/mmio: Add sysfs reporting for Processor MMIO Stale Data x86/speculation/srbds: Update SRBDS mitigation selection x86/speculation/mmio: Reuse SRBDS mitigation for SBDS
KVM: x86/speculation: Disable Fill buffer clear within guests
Tony Luck (1):
x86/cpu: Add Lakefield, Alder Lake and Rocket Lake models to the to Intel CPU family
Zhang Rui (1):
x86/cpu: Add Jasper Lake to Intel family
Greg Kroah-Hartman
maintainerDocumentation/ABI/testing/sysfs-devices-system-cpu +1 -0
@@ -489,6 +489,7 @@ What: /sys/devices/system/cpu/vulnerabilities /sys/devices/system/cpu/vulnerabilities/srbds /sys/devices/system/cpu/vulnerabilities/tsx_async_abort /sys/devices/system/cpu/vulnerabilities/itlb_multihit + /sys/devices/system/cpu/vulnerabilities/mmio_stale_data Date: January 2018 Contact: Linux kernel mailing list <[email protected]> Description: Information about CPU vulnerabilities
Documentation/admin-guide/hw-vuln/index.rst +1 -0
@@ -15,3 +15,4 @@ are configurable at compile, boot or run time. tsx_async_abort multihit.rst special-register-buffer-data-sampling.rst + processor_mmio_stale_data.rst
Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst new file +246 -0
246 lines not on this page · raw message
Documentation/admin-guide/kernel-parameters.txt +36 -0
@@ -2681,6 +2681,7 @@ kvm.nx_huge_pages=off [X86] no_entry_flush [PPC] no_uaccess_flush [PPC] + mmio_stale_data=off [X86] Exceptions: This does not have any effect on
@@ -2702,6 +2703,7 @@ Equivalent to: l1tf=flush,nosmt [X86] mds=full,nosmt [X86] tsx_async_abort=full,nosmt [X86] + mmio_stale_data=full,nosmt [X86] mminit_loglevel= [KNL] When CONFIG_DEBUG_MEMORY_INIT is set, this
@@ -2711,6 +2713,40 @@ log everything. Information is printed at KERN_DEBUG so loglevel=8 may also need to be specified. + mmio_stale_data= + [X86,INTEL] Control mitigation for the Processor + MMIO Stale Data vulnerabilities. + + Processor MMIO Stale Data is a class of + vulnerabilities that may expose data after an MMIO + operation. Exposed data could originate or end in + the same CPU buffers as affected by MDS and TAA. + Therefore, similar to MDS and TAA, the mitigation + is to clear the affected CPU buffers. + + This parameter controls the mitigation. The + options are: + + full - Enable mitigation on vulnerable CPUs + + full,nosmt - Enable mitigation and disable SMT on + vulnerable CPUs. + + off - Unconditionally disable mitigation + + On MDS or TAA affected machines, + mmio_stale_data=off can be prevented by an active + MDS or TAA mitigation as these vulnerabilities are + mitigated with the same mechanism so in order to + disable this mitigation, you need to specify + mds=off and tsx_async_abort=off too. + + Not specifying this option is equivalent to + mmio_stale_data=full. + + For details see: + Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst + module.sig_enforce [KNL] When CONFIG_MODULE_SIG is set, this means that modules without (valid) signatures will fail to load.
Makefile +1 -1
@@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 5 PATCHLEVEL = 4 -SUBLEVEL = 198 +SUBLEVEL = 199 EXTRAVERSION = NAME = Kleptomaniac Octopus
arch/x86/include/asm/cpufeatures.h +1 -0
@@ -405,5 +405,6 @@#define X86_BUG_TAA X86_BUG(22)/* CPU is affected by TSX Async Abort(TAA) */ #define X86_BUG_ITLB_MULTIHIT X86_BUG(23)/* CPU may incur MCE during certain page attribute changes */ #define X86_BUG_SRBDS X86_BUG(24)/* CPU may leak RNG bits if not mitigated */ +#define X86_BUG_MMIO_STALE_DATA X86_BUG(25)/* CPU is affected by Processor MMIO Stale Data vulnerabilities */ #endif /* _ASM_X86_CPUFEATURES_H */
arch/x86/include/asm/intel-family.h +9 -0
@@ -86,6 +86,14 @@#define INTEL_FAM6_COMETLAKE 0xA5#define INTEL_FAM6_COMETLAKE_L 0xA6 +#define INTEL_FAM6_ROCKETLAKE 0xA7 + +/* Hybrid Core/Atom Processors */ + +#define INTEL_FAM6_LAKEFIELD 0x8A +#define INTEL_FAM6_ALDERLAKE 0x97 +#define INTEL_FAM6_ALDERLAKE_L 0x9A +/* "Small Core" Processors (Atom) */ #define INTEL_FAM6_ATOM_BONNELL 0x1C/* Diamondville, Pineview */
@@ -111,6 +119,7 @@#define INTEL_FAM6_ATOM_TREMONT_D 0x86/* Jacobsville */ #define INTEL_FAM6_ATOM_TREMONT 0x96/* Elkhart Lake */ +#define INTEL_FAM6_ATOM_TREMONT_L 0x9C/* Jasper Lake */ /* Xeon Phi */
arch/x86/include/asm/msr-index.h +25 -0
@@ -105,6 +105,30 @@* Not susceptible to * TSX Async Abort (TAA) vulnerabilities. */ +#define ARCH_CAP_SBDR_SSDP_NO BIT(13)/* +* Not susceptible to SBDR and SSDP +* variants of Processor MMIO stale data +* vulnerabilities. +*/ +#define ARCH_CAP_FBSDP_NO BIT(14)/* +* Not susceptible to FBSDP variant of +* Processor MMIO stale data +* vulnerabilities. +*/ +#define ARCH_CAP_PSDP_NO BIT(15)/* +* Not susceptible to PSDP variant of +* Processor MMIO stale data +* vulnerabilities. +*/ +#define ARCH_CAP_FB_CLEAR BIT(17)/* +* VERW clears CPU fill buffer +* even on MDS_NO CPUs. +*/ +#define ARCH_CAP_FB_CLEAR_CTRL BIT(18)/* +* MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS] +* bit available to control VERW +* behavior. +*/ #define MSR_IA32_FLUSH_CMD 0x0000010b#define L1D_FLUSH BIT(0)/*
@@ -122,6 +146,7 @@/* SRBDS support */ #define MSR_IA32_MCU_OPT_CTRL 0x00000123#define RNGDS_MITG_DIS BIT(0) +#define FB_CLEAR_DIS BIT(3)/* CPU Fill buffer clear disable */ #define MSR_IA32_SYSENTER_CS 0x00000174#define MSR_IA32_SYSENTER_ESP 0x00000175
arch/x86/include/asm/nospec-branch.h +2 -0
@@ -313,6 +313,8 @@ DECLARE_STATIC_KEY_FALSE(switch_mm_always_ibpb);DECLARE_STATIC_KEY_FALSE (mds_user_clear);DECLARE_STATIC_KEY_FALSE (mds_idle_clear); +DECLARE_STATIC_KEY_FALSE (mmio_stale_data_clear); +#include <asm/segment.h> /**
arch/x86/kernel/cpu/bugs.c +199 -36
334 lines not on this page · raw message
arch/x86/kernel/cpu/common.c +49 -3
85 lines not on this page · raw message
arch/x86/kvm/vmx/vmx.c +74 -1
121 lines not on this page · raw message
arch/x86/kvm/vmx/vmx.h +3 -0
@@ -280,8 +280,11 @@ struct vcpu_vmx {u64 msr_ia32_feature_control;u64 msr_ia32_feature_control_valid_bits;u64 ept_pointer; +u64 msr_ia32_mcu_opt_ctrl; +bool disable_fb_clear;struct pt_desc pt_desc; + };enum ept_pointers_status {
arch/x86/kvm/x86.c +4 -0
@@ -1403,6 +1403,10 @@ static u64 kvm_get_arch_capabilities(void)/* KVM does not emulate MSR_IA32_TSX_CTRL. */ data &= ~ARCH_CAP_TSX_CTRL_MSR ; + +/* Guests don't need to know "Fill buffer clear control" exists */ + data &= ~ARCH_CAP_FB_CLEAR_CTRL ; +return data; }
drivers/base/cpu.c +8 -0
@@ -568,6 +568,12 @@ ssize_t __weak cpu_show_srbds(struct device *dev,return sysfs_emit (buf,"Not affected\n" ); } +ssize_t __weak cpu_show_mmio_stale_data (struct device *dev, +struct device_attribute *attr,char *buf) +{ +return sysfs_emit (buf,"Not affected\n" ); +} + static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL); static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL); static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL);
@@ -577,6 +583,7 @@ static DEVICE_ATTR(mds, 0444, cpu_show_mds, NULL); static DEVICE_ATTR(tsx_async_abort, 0444, cpu_show_tsx_async_abort, NULL); static DEVICE_ATTR(itlb_multihit, 0444, cpu_show_itlb_multihit, NULL); static DEVICE_ATTR(srbds, 0444, cpu_show_srbds, NULL); +static DEVICE_ATTR(mmio_stale_data, 0444, cpu_show_mmio_stale_data, NULL);static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_meltdown.attr,
@@ -588,6 +595,7 @@ static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_tsx_async_abort.attr, &dev_attr_itlb_multihit.attr, &dev_attr_srbds.attr, + &dev_attr_mmio_stale_data.attr, NULL };
include/linux/cpu.h +4 -0
@@ -64,6 +64,10 @@ extern ssize_t cpu_show_tsx_async_abort(struct device *dev, char *buf);extern ssize_t cpu_show_itlb_multihit (struct device *dev,struct device_attribute *attr,char *buf); +extern ssize_t cpu_show_srbds (struct device *dev,struct device_attribute *attr,char *buf); +extern ssize_t cpu_show_mmio_stale_data (struct device *dev, +struct device_attribute *attr, +char *buf); extern __printf(4, 5) struct device *cpu_device_create(struct device *parent, void *drvdata,