FAILED: patch "[PATCH] drm/i915/slpc: Let's fix the PCODE min freq table setup for" failed to apply to 5.15-stable tree

The patch below does not apply to the 5.15-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

Possible dependencies:

e1cab970574c ("drm/i915/slpc: Let's fix the PCODE min freq table setup for SLPC") 4dd4375bc4ff ("drm/i915: split out intel_pcode.[ch] to separate file") 1eecf31e3c96 ("drm/i915: split out vlv sideband to a separate file") 5f5ada0bae45 ("drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels()") 193299ad9d85 ("drm/i915: Nuke useless .set_signal_levels() wrappers") e722ab8b6968 ("drm/i915: Generalize .set_signal_levels()") 5bafd85dd770 ("drm/i915: Introduce has_buf_trans_select()") f820693bc238 ("drm/i915: Introduce has_iboost()")
80e77e30a212 ("drm/i915/dpll: move dpll modeset asserts to intel_dpll.c") aa0813b1ba31 ("drm/i915/pps: move pps (panel) modeset asserts to intel_pps.c") e04a911f4366 ("drm/i915/fdi: move fdi modeset asserts to intel_fdi.c") e505d76404b1 ("drm/i915: s/ddi_translations/trans/")
4360a2b54fd7 ("drm/i915/display: add intel_fdi_link_train wrapper.") 8c66081b0b32 ("drm/i915: s/pipe/transcoder/ when dealing with PIPECONF/TRANSCONF") a338847abc8e ("drm/i915: Call {vlv,chv}_prepare_pll() from {vlv,chv}_enable_pll()") 510e890e8222 ("drm/i915: Remove the 'reg' local variable") 8a3b3df39757 ("drm/i915: Clean up variable names in old dpll functions") 6205372b4b6d ("drm/i915: Clean dpll calling convention")
24951b5813c1 ("drm/i915: Constify struct dpll all over")
b294425e9091 ("drm/i915: Extract ilk_update_pll_dividers()")

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From e1cab970574c001d83e59ca8388c474a57a1afb6 Mon Sep 17 00:00:00 2001
From: Rodrigo Vivi <[email protected]>
Date: Wed, 31 Aug 2022 17:45:38 -0400
Subject: [PATCH] drm/i915/slpc: Let's fix the PCODE min freq table setup for
SLPC

We need to inform PCODE of a desired ring frequencies so PCODE update the memory frequencies to us. rps->min_freq and rps->max_freq are the frequencies used in that request. However they were unset when SLPC was enabled and PCODE never updated the memory freq.

v2 (as Suggested by Ashutosh): if SLPC is in use, let's pick the right
frequencies from the get_ia_constants instead of the fake init of rps' min and max.

v3: don't forget the max <= min return

v4: Move all the freq conversion to intel_rps.c. And the max <= min
check to where it belongs.

v5: (Ashutosh) Fix old comment s/50 HZ/50 MHz and add a doc explaining
the "raw format"

index 14fe65812e42..1d19c073ba2e 100644
@@ -12,6 +12,7 @@
 #include "intel_llc.h"
 #include "intel_mchbar_regs.h"
 #include "intel_pcode.h"
+#include "intel_rps.h"
 
 struct ia_constants {
 	unsigned int min_gpu_freq;

@@ -55,9 +56,6 @@ static bool get_ia_constants(struct intel_llc *llc,
 	if (!HAS_LLC(i915) || IS_DGFX(i915))
 		return false;
 
-	if (rps->max_freq <= rps->min_freq)
-		return false;
-
 	consts->max_ia_freq = cpu_max_MHz();
 
 	consts->min_ring_freq =

@@ -65,13 +63,8 @@ static bool get_ia_constants(struct intel_llc *llc,
 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 	consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
 
-	consts->min_gpu_freq = rps->min_freq;
-	consts->max_gpu_freq = rps->max_freq;
-	if (GRAPHICS_VER(i915) >= 9) {
-		/* Convert GT frequency to 50 HZ units */
-		consts->min_gpu_freq /= GEN9_FREQ_SCALER;
-		consts->max_gpu_freq /= GEN9_FREQ_SCALER;
-	}
+	consts->min_gpu_freq = intel_rps_get_min_raw_freq(rps);
+	consts->max_gpu_freq = intel_rps_get_max_raw_freq(rps);
 
 	return true;
 }

@@ -130,6 +123,12 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
 	if (!get_ia_constants(llc, &consts))
 		return;
 
+	/*
+	 * Although this is unlikely on any platform during initialization,
+	 * let's ensure we don't get accidentally into infinite loop
+	 */
+	if (consts.max_gpu_freq <= consts.min_gpu_freq)
+		return;
 	/*
 	 * For each potential GPU frequency, load a ring frequency we'd like
 	 * to use for memory access.  We do this by specifying the IA frequency

index 1e8d56491308..4509dfdc52e0 100644
@@ -37,8 +37,10 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1);
 u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
 u32 intel_rps_get_requested_frequency(struct intel_rps *rps);
 u32 intel_rps_get_min_frequency(struct intel_rps *rps);
+u32 intel_rps_get_min_raw_freq(struct intel_rps *rps);
 int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val);
 u32 intel_rps_get_max_frequency(struct intel_rps *rps);
+u32 intel_rps_get_max_raw_freq(struct intel_rps *rps);
 int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val);
 u32 intel_rps_get_rp0_frequency(struct intel_rps *rps);
 u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);